Characterization of the Vertical Position of the Trapped Charge in Charge-trap Flash Memory

김승현,권대웅,이상호,박상구,김영민,김형민,김영건,조성재,박병국 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.2

In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.

Organic nonvolatile memory devices utilizing intrinsic charge-trapping phenomena in an n-type polymer semiconductor

Murari, N.M.,Hwang, Y.J.,Kim, F.S.,Jenekhe, S.A. Elsevier Science 2016 ORGANIC ELECTRONICS Vol.31 No.-

<P>Charge trapping is an undesirable phenomenon and a common challenge in the operation of n-channel organic field-effect transistors. Herein, we exploit charge trapping in an n-type semiconducting poly (naphthalene diimide-alt-biselenophene) (PNDIBS) as the key operational mechanism to develop high performance, nonvolatile, electronic memory devices. The PNDIBS-based field-effect transistor memory devices were programmed at 60 V and they showed excellent charge-trapping and de-trapping characteristics, which could be cycled more than 200 times with a current ratio of 10(3) between the two binary states. Programmed data could be retained for 10(3) s with a memory window of 28 V. This is a record performance for n-channel organic transistor with inherent charge-trapping capability without using external charge trapping agents. However, the memory device performance was greatly reduced, as expected, when the n-type polymer semiconductor was end-capped with phenyl groups to reduce the trap density. These results show that the trap density of n-type semiconducting polymers could be engineered to control the inherent charge-trapping capability and device performance for developing high-performance low-cost memory devices. (c) 2016 Elsevier B.V. All rights reserved.</P>

Characterization of the Vertical Position of the Trapped Charge in Charge-trap Flash Memory

Seunghyun Kim,Dae Woong Kwon,Sang-Ho Lee,Sang-Ku Park,Youngmin Kim,Hyungmin Kim,Young Goan Kim,Seongjae Cho,Byung-Gook Park 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.2

In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.

Charge Pumping Method를 이용한 Silicon-Al2O3-Nitride- Oxide-Silicon Flash Memory Cell Transistor의 트랩과 소자 특성 분석

박성수(Sung-Soo Park),최원호(Won-Ho Choi),한인식(In-Shik Han),나민기(Min-Gi Na),이가원(Ga-Won Lee) 대한전자공학회 2008 電子工學會論文誌-SD (Semiconductor and devices) Vol.45 No.7

본 논문에서는 전하 펌프 방법 (Charge Pumping Method, CPM)를 이용하여 서로 다른 질화막 층을 가지는 N-Channel SANOS (Silicon-Al₂O₃-Nitride-Oxide-Silicon) Flash Memory Cell 트랜지스터의 트랩 특성을 규명하였다. SANOS Flash Memory에서 계면 및 질화막 트랩의 중요성은 널리 알려져 있지만, 소자에 직접 적용 가능하면서 정확하고 용이한 트랩 분석 방법은 미흡하다고 할 수 있다. 기존에 알려진 분석 방법 중 전하 펌프 방법은 측정 및 분석이 간단하면서 트랜지스터에 직접 적용이 가능하여 MOSFET에 널리 사용되어왔으며 최근에는 MONOS/SONOS 구조에도 적용되고 있지만 아직까지는 Silicon 기판과 tunneling oxide와의 계면에 존재하는 트랩 및 tunneling oxide가 얇은 구조에서의 질화막 벌크 트랩 추출 결과만이 보고되어 있다. 이에 본 연구에서는 Trapping Layer (질화막)가 다른 SONOS 트랜지스터에 전하 펌프 방법을 적용하여 Si 기판/Tunneling Oxide 계면 트랩 및 질화막 트랩을 분리하여 평가하였으며 추출된 결과의 정확성 및 유용성을 확인하고자 트랜지스터의 전기적 특성 및 메모리 특성과의 상관 관계를 분석하고 Simulation을 통해 확인하였다. 분석 결과 계면 트랩의 경우 트랩 밀도가 높고 trap의 capture cross section이 큰 소자의 경우 전자이동도, subthreshold slop, leakage current 등의 트랜지스터의 일반적인 특성 열화가 나타났다. 계면 트랩은 특히 Memory 특성 중 Program/Erase (P/E) speed에 영향을 미치는 것으로 나타났는데 이는 계면결함이 많은 소자의 경우 같은 P/E 조건에서 더 많은 전하가 계면결함에 포획됨으로써 trapping layer로의 carrier 이동이 억제되기 때문으로 판단되며 simulation을 통해 서도 동일한 결과를 확인하였다. 하지만 data retention의 경우 계면 트랩보다 charge trapping layer인 질화막 트랩 특성에 의해 더 크게 영향을 받는 것으로 나타났다. 이는 P/E cycling 횟수에 따른 data retention 특성 열화 측정 결과에서도 일관되게 확인할 수 있었다. In this paper, the dependence of electrical characteristics of Silicon-Al₂O₃-Nitride-Oxide -Silicon (SANOS) memory cell transistors and program/erase (P/E) speed, reliability of memory device on interface trap between Si substrate and tunneling oxide and bulk trap in nitride layer were investigated using charge pumping method which has advantage of simple and versatile technique. We analyzed different SANOS memory devices that were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SANOS cell transistors with larger capture cross section and interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. The data retention was deteriorated as increasing P/E cycling number but not coincides with interface trap increasing tendency. This result once again confirmed that interface trap independence on data retention. And the result on different program method shows that HCI program method more degraded by locally trapping. So, we know as a result of experimentthat analysis the SANOS Flash memory characteristic using charge pumping method reflect the device performance related to interface and bulk trap.

Characterization of the Vertical Position of the Trapped Charge in Charge-trap Flash Memory

Kim, Seunghyun,Kwon, Dae Woong,Lee, Sang-Ho,Park, Sang-Ku,Kim, Youngmin,Kim, Hyungmin,Kim, Young Goan,Cho, Seongjae,Park, Byung-Gook The Institute of Electronics and Information Engin 2017 Journal of semiconductor technology and science Vol.17 No.2

In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.

The electron trap parameter extraction-based investigation of the relationship between charge trapping and activation energy in IGZO TFTs under positive bias temperature stress

Rhee, Jihyun,Choi, Sungju,Kang, Hara,Kim, Jae-Young,Ko, Daehyun,Ahn, Geumho,Jung, Haesun,Choi, Sung-Jin,Myong Kim, Dong,Kim, Dae Hwan Elsevier 2018 Solid-State Electronics Vol.140 No.-

<P><B>Abstract</B></P> <P>Experimental extraction of the electron trap parameters which are associated with charge trapping into gate insulators under the positive bias temperature stress (PBTS) is proposed and demonstrated for the first time in amorphous indium-gallium-zinc-oxide thin-film transistors. This was done by combining the PBTS/recovery time-evolution of the experimentally decomposed threshold voltage shift (ΔV<SUB>T</SUB>) and the technology computer-aided design (TCAD)-based charge trapping simulation. The extracted parameters were the trap density (N<SUB>OT</SUB>) = 2.6×10<SUP>18</SUP> cm<SUP>−3</SUP>, the trap energy level (ΔE<SUB>T</SUB>) = 0.6 eV, and the capture cross section (σ<SUB>0</SUB>) = 3 × 10<SUP>−19</SUP> cm<SUP>2</SUP>.</P> <P>Furthermore, based on the established TCAD framework, the relationship between the electron trap parameters and the activation energy (E<SUB>a</SUB>) is comprehensively investigated. It is found that E<SUB>a</SUB> increases with an increase in σ<SUB>0</SUB>, whereas E<SUB>a</SUB> is independent of N<SUB>OT</SUB>. In addition, as ΔE<SUB>T</SUB> increases, E<SUB>a</SUB> decreases in the electron trapping-dominant regime (low ΔE<SUB>T</SUB>) and increases again in the Poole–Frenkel (PF) emission/hopping-dominant regime (high ΔE<SUB>T</SUB>). Moreover, our results suggest that the cross-over ΔE<SUB>T</SUB> point originates from the complicated temperature-dependent competition between the capture rate and the emission rate. The PBTS bias dependence of the relationship between E<SUB>a</SUB> and ΔE<SUB>T</SUB> suggests that the electric field dependence of the PF emission-based electron hopping is stronger than that of the thermionic field emission-based electron trapping.</P> <P><B>Highlights</B></P> <P> <UL> <LI> The use of ΔV<SUB>T</SUB> de-embedded from the measured PBTS ΔV<SUB>T</SUB> which is associated only with the charge trapping into gate insulator. </LI> <LI> Detailed and clear procedure of extracting the gate insulator electron trap parameters in IGZO thin-film transistors. </LI> <LI> Analysis of the relationship between activation energy and electron trap parameters. </LI> <LI> Useful in the joint-optimization of gate insulator and active films in highly stable IGZO thin-film transistors. </LI> </UL> </P>

Heavily Doped, Charge-Balanced Fluorescent Organic Light-Emitting Diodes from Direct Charge Trapping of Dopants in Emission Layer

Rhee, Sang Ho,Kim, Sung Hyun,Kim, Hwang Sik,Shin, Jun Young,Bastola, Jeeban,Ryu, Seung Yoon American Chemical Society 2015 ACS APPLIED MATERIALS & INTERFACES Vol.7 No.30

<P>We studied the effect of direct charge trapping at different doping concentrations on the device performance in tris(8-hydroxyquinoline) aluminum (Alq<SUB>3</SUB>):10-(2-benzothiazolyl)-2,3,6,7-tetrahydro-1,1,7,7-tetramethyl-1H,5H,11H-(1)-benzopyropyrano(6,7–8-i,j)quinolizin-11-one (C545T) as a host–dopant system of a fluorescent organic light-emitting diode. With increasing C545T doping concentration, trap sites could lead to the promotion of hole injection and the suppression of electron injection due to the electron-transport character of Alq<SUB>3</SUB> host for each carriers, as confirmed by hole- and electron-only devices. Direct charge injection of hole carriers from the hole transport layer into C545T dopants and the charge trapping of electron carriers are the dominant processes to improve the charge balance and the corresponding efficiency. The shift of the electroluminescence (EL) spectra from 519 nm to 530 nm was confirmed the exciton formation route from Förster energy transfer of host–dopant system to direct charge trapping of dopant-only emitting systems. Variation in the doping concentration dictates the role of the dopant in the fluorescent host–dopant system. Even though concentration quenching in fluorescent dopants is unavoidable, relatively heavy doping is necessary to improve the charge balance and efficiency and to investigate the relationship between direct charge trapping and device performance. Heavy doping at a doping ratio of 6% also generates heavy exciton quenching and excimer exciton, because of the excitons being close enough and dipole–dipole interactions. The optimum device performance was achieved with a 4%-doped device, retaining the high efficiency of 12.5 cd/A from 100 cd/m<SUP>2</SUP> up to 15 000 cd/m<SUP>2</SUP>.</P><P><B>Graphic Abstract</B> <IMG SRC='http://pubs.acs.org/appl/literatum/publisher/achs/journals/content/aamick/2015/aamick.2015.7.issue-30/acsami.5b04519/production/images/medium/am-2015-045192_0011.gif'></P><P><A href='http://pubs.acs.org/doi/suppl/10.1021/am5b04519'>ACS Electronic Supporting Info</A></P>

Charge-trapping memory device based on a heterostructure of MoS2 and CrPS4

Shin Minjeong,이미정,윤찬수,Kim Sohwi,Park Bae Ho,이성민,박재근 한국물리학회 2021 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.78 No.9

Atomically thin two-dimensional (2D) materials have emerged as promising candidates for flexible and transparent electronic applications. Here, we introduce non-volatile charge trapping memory devices, based on the 2D heterostructure field-effect transistor consisting of a few-layer MoS2 channel and CrPS4 charge-trapping gate stack. Clockwise hysteresis behaviors in transfer curves measured at room temperature show strong dependence on the thickness of CrPS4, which are attributed to charge trapping at trap sites in the CrPS4 layers. Our heterostructure memory device with 75 nm-thick CrPS4 layer exhibits both large memory windows up to 100 V and a high on/of current ratio (3 × 105 ) with good endurance during 625 cycles because of excellent trapping ability of trap sites in the CrPS4. Especially, the memory window size can be effectively tuned from 7.6 to 100 V by changing the sweep range of gate voltage. Such high performances of the charge-trapping memory device with a simple heterostructure provide a promising route towards next-generation memory devices utilizing 2D materials.

Impact of Charge-Trap Layer Conductivity Control on Device Performances of Top-Gate Memory Thin-Film Transistors Using IGZO Channel and ZnO Charge-Trap Layer

Jun Yong Bak,Min-Ki Ryu,Sang Hee Ko Park,Chi-Sun Hwang,Sung Min Yoon Institute of Electrical and Electronics Engineers 2014 IEEE transactions on electron devices Vol. No.

<P>A top-gate-structured charge-trap-type memory thin-film transistors (CTM-TFTs) using In-Ga-Zn-O (IGZO) channel and ZnO charge-trap layers were proposed to investigate effects of conductivity modulation for charge-trap layers on the memory performances. The electrical conductivity of ZnO charge-trap layers were controlled by varying the deposition temperatures to 100 °C (CTM1), 150 °C (CTM2), and 200 °C (CTM3) during the atomic layer deposition process and this strategy was well confirmed in the controlled devices using the conductivity-modulated ZnO channel layers. The IGZO TFT without charge-trap layer was also evaluated to have excellent device characteristics thanks to the high-quality interface between IGZO and Al<SUB>2</SUB>O<SUB>3</SUB> tunneling layer. The CTM1 and CMT2 exhibited a wide memory window (MW), sufficiently high program speed, and strong endurance properties. However, these promising memory behaviors could not be obtained for the CTM3 owing to its highly conductive charge-trap layer. For the evaluation of retention properties, there were big difference between the CTM1 and CTM2. Consequently, the CTM1 exhibited best memory performances. The MW and the memory margin in programmed current (ION/OFF) were estimated to be 17.1 V, and 1.3 × 10<SUP>8</SUP>, respectively. The I<SUB>ON/OFF</SUB> was obtained to be 2.6 × 10<SUP>6</SUP> and 1.8 × 10<SUP>3</SUP> after the 10<SUP>4</SUP> times cyclic operations and after the retention test for 10<SUP>4</SUP> s, respectively.</P>

Investigation of the Channel-Width Dependence of CHEI Program/HHI Erase Cycling Behavior in Nitride-Based Charge-Trapping Flash (CTF) Memory Devices

Seung-Hwan Seo,김대환,Chang-Min Choi,김동명,Gu-Cheol Kang,Jang-Uk Lee,Jun-Hyun Park,Kang-Seob Roh,Ki-Chan Jeon,Kwan-Jae Song,Kwan-Young Kim,Se-Woon Kim,Soon-Young Lee,So-Ra Park 한국물리학회 2008 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.52 No.2

The channel-width dependence of program/erase cycling behavior in nitride-based charge-trap flash memory devices is investigated. When the program/erase is conducted by a channel-hot-electron-injection (CHEI) program/hot-hole-injection (HHI) erase, respectively, while a trapped-charge-profile-dependent overerasure is observed clearly in a wide device, it is suppressed in a narrow device. The channel-width dependence is featured in both the overerasure suppression and the gradual positive shift of the threshold voltage in narrow devices. This is explained as an elevated hot-hole-injection erase efficiency in the channel-center region and a suppression of the lateral migration of injected holes in the channel-edge region by combining the measured endurance characteristics and Technology Computer-Aided Designs (TCAD) device simulation results. The main physical mechanisms are the three-dimensional distribution of the electric field by gate/drain voltage, increasing interface states, and their trapped charge during program/erase cycling in the channel-edge region. The channel-width dependence of program/erase cycling behavior in nitride-based charge-trap flash memory devices is investigated. When the program/erase is conducted by a channel-hot-electron-injection (CHEI) program/hot-hole-injection (HHI) erase, respectively, while a trapped-charge-profile-dependent overerasure is observed clearly in a wide device, it is suppressed in a narrow device. The channel-width dependence is featured in both the overerasure suppression and the gradual positive shift of the threshold voltage in narrow devices. This is explained as an elevated hot-hole-injection erase efficiency in the channel-center region and a suppression of the lateral migration of injected holes in the channel-edge region by combining the measured endurance characteristics and Technology Computer-Aided Designs (TCAD) device simulation results. The main physical mechanisms are the three-dimensional distribution of the electric field by gate/drain voltage, increasing interface states, and their trapped charge during program/erase cycling in the channel-edge region.