Light Effect on Negative Bias-Induced Instability of HfInZnO Amorphous Oxide Thin-Film Transistor

Dae Woong Kwon,Jang Hyun Kim,Ji Soo Chang,Sang Wan Kim,Wandong Kim,Jae Chul Park,Chang Jung Kim,Byung-Gook Park IEEE 2011 IEEE transactions on electron devices Vol.58 No.4

<P>For the first time, a comprehensive study is done regarding the stability under simultaneous application of light and gate dc bias in amorphous hafnium-indium-zinc-oxide (α-HIZO) thin-film transistors (TFTs). Subthreshold swing (SS) degradation, a negative threshold voltage (V<SUB>th</SUB>) shift, and the occurrence of hump are observed in transfer curves after applying a negative gate bias and light stress. Based on the retention test at room temperature and the hysteresis analysis, it is revealed that all these phenomena result from hole trapping in the gate insulator. Moreover, it is proven that the SS degradation and hump occurrence are mainly attributed to hole trapping in SiO<SUB>2</SUB> at the edge regions along the channel length/width directions and that a negative V<SUB>th</SUB> shift is derived from hole trapping in the gate insulator far from the SiO<SUB>2</SUB>/HIZO interface.</P>

A novel fabrication method for co-integrating ISFET with damage-free sensing oxide and threshold voltage-tunable CMOS read-out circuits

Kwon, Dae Woong,Lee, Ryoongbin,Kim, Sihyun,Mo, Hyun-Sun,Kim, Dae Hwan,Park, Byung-Gook Elsevier 2018 Sensors and actuators. B Chemical Vol.260 No.-

<P><B>Abstract</B></P> <P>A novel fabrication method using a top SiO<SUB>2</SUB>-SiN-bottom SiO<SUB>2</SUB> (ONO) dielectric stack is proposed and implemented to obtain ion sensitive field effect transistor (ISFET) with damage-free sensing oxide and threshold voltage (<I>V</I> <SUB>th</SUB>)-tunable devices in CMOS read-out circuits. By wet-etching the top SiO<SUB>2</SUB> and the SiN sequentially, the ISFET with damage-free sensing oxide is obtained due to the high selectivity between them. Also, the <I>V</I> <SUB>th</SUB>-tunable circuit devices with the ONO stacks are simultaneously achieved by protecting the ONO stacks from the wet-etching. Through the measurements of pH and biomolecule responses, it is confirmed that the pH and biomolecule can be detected stably because the drain current (<I>I</I> <SUB>D</SUB>) is stabilized to a predetermined value more quickly and the <I>I</I> <SUB>D</SUB> fluctuation during the <I>I</I> <SUB>D</SUB> stabilization is significantly reduced compared with devices having damaged sensing oxide. Additionally, it is verified that the <I>V</I> <SUB>th</SUB> of devices for circuits can be fine-controlled by injecting charges into the SiN via Fowler-Nordheim tunneling. Furthermore, it is demonstrated that the biomolecule-induced <I>V</I> <SUB>th</SUB> shift of ∼150 mV in the proposed ISFET is successfully amplified to the output voltage change of ∼370 mV in common source amplifier (CSA) voltage-readout circuit consisting of one p-type ISFET and one <I>V</I> <SUB>th</SUB>-tuned n-type MOS.</P> <P><B>Highlights</B></P> <P> <UL> <LI> The damage-free sensing oxide is obtained using top SiO<SUB>2</SUB>-SiN-bottom SiO<SUB>2</SUB> (ONO) dielectric stack in the proposed ISFET. </LI> <LI> The drift and fluctuation of the drain current are significantly reduced by the damage-free sensing oxide. </LI> <LI> The threshold voltage (<I>V</I> <SUB>th</SUB>)-tunable CMOS read-out circuits are simultaneously obtained with the ISFET by using the ONO stack. </LI> <LI> The biomolecule sensing system consisting of the proposed ISFET and <I>V</I> <SUB>th</SUB>-tunable CMOS read-out circuits is demonstrated. </LI> </UL> </P>

Reduction method of gate-to-drain capacitance by oxide spacer formation in tunnel field-effect transistor with elevated drain

Kwon, Dae Woong,Kim, Jang Hyun,Park, Euyhwan,Lee, Junil,Park, Taehyung,Lee, Ryoongbin,Kim, Sihyun,Park, Byung-Gook Institute of Pure and Applied Physics 2016 Japanese Journal of Applied Physics Vol.55 No.6

<P>A novel fabrication method is proposed to reduce large gate-to-drain capacitance (CGD) and to improve AC switching characteristics in tunnel field-effect transistor (TFETs) with elevated drain (TFETED). In the proposed method, gate oxide at drain region (GDOX) is selectively formed through oxide deposition and spacer-etch process. Furthermore, the thicknesses of the GDOX are simply controlled by the amount of the oxide deposition and etch. Mixed-mode device and circuit technology computer aided design (TCAD) simulations are performed to verify the effects of the GDOX thickness on DC and AC switching characteristics of a TFETED inverter. As a result, it is found that AC switching characteristics such as output voltage pre-shoot and falling/rising delay are improved with nearly unchanged DC characteristics by thicker GDOX. This improvement is explained successfully by reduced CGD and positive shifted gate voltage (VG) versus CGD curves with the thicker GDOX. (C) 2016 The Japan Society of Applied Physics</P>

Effects of Localized Body Doping on Switching Characteristics of Tunnel FET Inverters With Vertical Structures

Kwon, Dae Woong,Kim, Hyun Woo,Kim, Jang Hyun,Park, Euyhwan,Lee, Junil,Kim, Wandong,Kim, Sangwan,Lee, Jong-Ho,Park, Byung-Gook IEEE 2017 IEEE transactions on electron devices Vol.64 No.4

<P>In order to verify the effects of localized body doping (LBD) on alternating current switching performances of tunnel FETs (TFETs) with vertical structures, The TFET inverter composed of n-/p-type TFET with the localized p(+)/n(+) body doping is simulated with the help of mixed-mode device and circuit simulations. As a result, falling/rising delay is significantly improved due to the locally high channel-to-drain side energy barrier induced by the LBD. Furthermore, LBD conditions, such as doping concentration, depth, and width, are optimized to maximize the improvement of falling/rising delay. Based on the optimization results, it is found that enough wide doping width and deep depth are inevitable to minimize the drain voltage (V-D)-induced lowering of the locally increased barrier and the increase of ambipolar current and toowide doping width cannot be applied due to the ON-current reduction caused by the degraded controllability of gate voltage on channel similarly to short channel effects. Moreover, the doping width and depth should be adjusted according to LBD concentration.</P>

Channel-Stacked NAND Flash Memory With Tied Bit-Line and Ground Select Transistor

Kwon, Dae Woong,Seo, Joo Yun,Park, Se Hwan,Kim, Wandong,Kim, Do-Bin,Lee, Sang-Ho,Cho, Gyu Seong,Park, Sung-Kye,Park, Byung-Gook IEEE 2016 IEEE electron device letters Vol.37 No.11

<P>In this letter, a channel-stacked array with tied bit-line (BL) and ground select transistor (GST) is proposed to access each layer independently without additional string select transistors (SSTs) to a conventional planar NAND array. The proposed structure can maximize memory density, since additional SSTs are not required for layer selection and the placement of BLs/word lines is similar to that of the conventional NAND array except for island-type GSTs. Basic memory operations are performed with fabricated devices. The selected layer is erased only by applying erase voltage to the selected common source line (CSL) and by biasing inhibition voltage to other CSLs. Only the selected layer is read by applying the same voltage as BL voltage to the CSLs of the unselected layers. In addition, the selected strings in the selected layer are programmed and other strings in the selected and unselected layers are all inhibited by the combination of CSL and BL voltages. Consequently, stable memory operations are obtained successfully in the proposed structure without interference between stacked layers.</P>

Novel Program Method of String Select Transistors for Layer Selection in Channel-Stacked NAND Flash Memory

Kwon, Dae Woong,Kim, Wandong,Kim, Do-Bin,Lee, Sang-Ho,Seo, Joo Yun,Choi, Eunseok,Cho, Gyu Seog,Park, Sung-Kye,Lee, Jong-Ho,Park, Byung-Gook IEEE 2016 IEEE transactions on electron devices Vol.63 No.9

<P>In this paper, we propose new string select transistors (SSTs)/dummy SSTs (DSSTs) threshold voltage (V-th) setting methods in simplified channel-stacked array with layer selection by multilevel operation (SLSM). In these methods, SSTs/DSSTs on each layer are set to their targeted V-th values by incremental step pulse program/one erase with various erase voltages, respectively. In the fabricated pseudo-SLSM, the validity of the new methods is verified. As a result, it is confirmed that the V-th values of SSTs/DSSTs are set to the targeted V-th values by the new methods and SSTs with extremely narrow V-th distribution can be obtained in the consequence. Moreover, memory operations such as erase, program, and read are performed in the fabricated structure after setting the V-th values of all the SSTs/DSSTs by the new methods. Despite unique LSM operations, stable memory operations are obtained successfully without the interference between stacked layers.</P>

Analysis on Program Disturbance in Channel-Stacked NAND Flash Memory With Layer Selection by Multilevel Operation

Dae Woong Kwon,Wandong Kim,Do-Bin Kim,Sang-Ho Lee,Joo Yun Seo,Myung-Hyun Baek,Ji-Ho Park,Eunseok Choi,Gyu Seong Cho,Sung-Kye Park,Jong-Ho Lee,Byung-Gook Park IEEE 2016 IEEE transactions on electron devices Vol.63 No.3

<P>Program disturbance is analyzed in a simplified channel-stacked array with layer selection by multilevel operation after setting the threshold voltages (V-th) of string select transistors (SSTs)/dummy SSTs. There are additional unselected cells that should be inhibited in different ways, and they have the worse disturbance characteristics compared with conventional NAND arrays. Technology computer-aided design simulations and measurements are performed to investigate the disturbance mechanism of the additional cases. It is found that initially nonprecharged channel and large leakage current flowing from channel to bitline degrade the disturbance. New program method is proposed along with low gate bias of dummy wordline. As a result, program disturbance is significantly improved and reliability is also enhanced by reducing the potential difference between the SST gate and the channel.</P>

Effects of drain doping concentration on switching characteristics of tunnel field-effect transistor inverters

Kwon, Dae Woong,Kim, Jang Hyun,Park, Byung-Gook IOP Publishing 2016 Japanese journal of applied physics Vol.55 No.11

<P>In order to investigate the effects of the modulation of drain doping concentration (N-drain) on alternating current (AC) switching characteristics of a tunnel filed-effect transistor (TFET) inverter, the characteristics of TFETs with various N(drain)s are analyzed rigorously through mixed-mode device and circuit TCAD simulations. As the N-drain gets decreased, the drain current (I-D) becomes reduced and the gate-to-drain capacitance (C-GD) reflects the entire gate capacitance (C-GG) at a lower gate voltage (V-G), which leads to the degradation of falling/rising delay in TFET inverters. These phenomena are explained successfully by the change of quasi-Fermi energy in the drain (E-F_drain) as a function of V-G. The E-F_drain rises dramatically from when tunneling current starts to flow from the source in the n-type TFET with low N-drain. As a result, drain-side channel inversion occurs at a lower V-G due to the reduction of the energy barrier between the E-F_drain and the conduction band edge of the channel. (C) 2016 The Japan Society of Applied Physics</P>

Analysis on Trapping Kinetics of Stress-Induced Trapped Holes in Gate Dielectric of Amorphous HfInZnO TFT

Dae Woong Kwon,Jang Hyun Kim,Wandong Kim,Sang Wan Kim,Jong-Ho Lee,Byung-Gook Park IEEE 2016 IEEE transactions on electron devices Vol.63 No.6

<P>A comprehensive study was done regarding stability under simultaneous stress of light and negative gate dc bias in amorphous hafnium-indium-zinc-oxide (alpha-HIZO) thin-film transistors. A negative threshold voltage (V-th) shift and an anomalous hump were observed in transfer characteristics after the stress, and it is explained that these phenomena are caused by the hole trapping in the SiO2 gate insulator, not by interface state generation. Furthermore, capacitance-voltage (C-G-V-G) measurements were performed with various frequencies to investigate the vertical distribution of the trapped holes in the gate insulator. As a result, the correlation between the vertical location of the trapped holes and the influence on C-G-V-G characteristics were revealed clearly. First, at the beginning of the stress, photogenerated holes are mainly trapped at the alpha-HIZO/SiO2 interface and interfacial SiO2 in contact with the interface, which induces the negative V-th shift. Second, as the stress time increases, the holes start to be trapped in the spatially deeper insulator, which leads to an additional hump in the C-G-V-G characteristics at sufficiently low frequencies.</P>

Tunnel field-effect transistor with asymmetric gate dielectric and body thickness

Kwon, Dae Woong,Park, Byung-Gook IOP Publishing 2017 Japanese journal of applied physics Vol.56 No.4

<P>Tunnel field-effect transistor (TFET) with asymmetric gate dielectric and body thickness (TFETAsy) is proposed. The TFETAsy not only reduces the tunneling resistance by using the thinner source-side gate dielectric and body, but also suppresses the ambipolar current (Iambipolar) and the degradation of alternating current (AC) switching performances with the thicker drain-side gate dielectric and body. Technology computer aided design process and device/circuit simulations are performed to verify the validity of the TFETAsy in terms of fabrication process and electrical characteristics. From the simulation results, it is revealed that the thinner source-side gate dielectric and body can be simply formed by oxide wetetching after the selective oxidation of the source-side body. Moreover, the thinner source-side SiGe body can be also formed by using Ge condensation process instead of the oxidation. Additionally, it is confirmed that the TFETAsy has higher on-current, steeper subthreshold swing, lower Iambipolar and improved AC switching characteristics as compared to those of conventional TFET with symmetric structure. (C) 2017 The Japan Society of Applied Physics</P>