Polyimide/polyvinyl alcohol bilayer gate insulator for low-voltage organic thin-film transistors

Yoo, Sungmi,Kim, Yun Ho,Ka, Jae-Won,Kim, Yong Seok,Yi, Mi Hye,Jang, Kwang-Suk Elsevier 2015 ORGANIC ELECTRONICS Vol.23 No.-

<P><B>Abstract</B></P> <P>In this paper, we report the fabrication of a polyimide/polyvinyl alcohol (PVA) bilayer gate insulator for low-voltage organic thin-film transistors (TFTs). The introduction of a PVA layer to form a bilayer structure improves the dielectric and insulating properties of the gate insulator. Organic TFTs with 150nm-thick polyimide and PVA gate insulators were inactive at low operation voltages below 5V. Conversely, organic TFTs with 150nm-thick polyimide/PVA bilayer gate insulators exhibited excellent device performances. Our results suggest that the introduction of a PVA layer with a high dielectric constant could be a simple and efficient way to improve the device performance of low-voltage organic TFTs.</P> <P><B>Highlights</B></P> <P> <UL> <LI> We report the polyimide/PVA bilayer gate insulator for low-voltage organic TFTs. </LI> <LI> Introduction of the PVA layer for forming the bilayer structure improves dielectric and insulating properties of the gate insulator. </LI> <LI> Pentacene and C<SUB>8</SUB>-BTBT TFTs with the 150nm-thick bilayer gate insulators exhibited excellent device performance. </LI> </UL> </P> <P><B>Graphical abstract</B></P> <P>[DISPLAY OMISSION]</P>

고성능 MISFET형 수소센서의 제작과 특성

강기호,박근용,한상도,최시영 한국수소및신에너지학회 2004 한국수소 및 신에너지학회논문집 Vol.15 No.4

We fabricated a MISFET using Pd/NiCr gate for the detecting of hydrogen gas in the air and investigated its electrical characteristics. To improve stability and high concenntration sensitivity and remove the blister generated by the penetration of hydrogen atoms Pd/NiCr catalyst gate metal are used as dual gate. To reduce the gate drift voltage caused by the inflow of hydrogen, the gate insulators of sensing and reference FFET were constructed with double insulation layers of silicon dioxide and silicon nitride. The hydrogen response of MISFET were amplified with the difference of gate voltages of both MISFET. To minimize the drift and the noise, we used a OP177 operational amplifier. The sensitivity of the Pd/NiCr gate MISFET was lower than that of Pd/Pt gate MISFET, but it showed good stability and ability to detect high concentration hydrogen up to 1000ppm.

Non-Overlapped Single/Double Gate SOI/GOI MOSFET for Enhanced Short Channel Immunity

Sharma, Sudhansh,Kumar, Pawan The Institute of Electronics and Information Engin 2009 Journal of semiconductor technology and science Vol.9 No.3

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

Non-Overlapped Single/Double Gate SOI/GOI MOSFET for Enhanced Short Channel Immunity

Sudhansh Sharma,Pawan Kumar 대한전자공학회 2009 Journal of semiconductor technology and science Vol.9 No.3

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon?on?Insulator (SOI) and Germanium?on?Insulator (GOI) MOSFETs. A design methodology, by evaluating the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non?overlapped gate?source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

One-pot surface modification of poly(ethylene-alt-maleic anhydride) gate insulators for low-voltage DNTT thin-film transistors

Yoo, S.,Yi, M.H.,Kim, Y.H.,Jang, K.S. Elsevier Science 2016 ORGANIC ELECTRONICS Vol.33 No.-

<P>This study investigates the one-pot surface modification of poly(ethylene-alt-maleic anhydride) (PEMA) gate insulators crosslinked with 1,5-naphthalenediamine (1,5-NDA) for enhancing the device performance of low-voltage dinaphtho[2,3-b:2',3'-f] thieno[3,2-b] thiophene (DNTT) organic thin-film transistors (OTFTs). Surface properties of the PEMA gate insulator could be easily modified by adding poly(maleic anhydride-alt-1-octadecene) (PMAO) to the coating solution. The surface energy of the gate insulator is strongly correlated with the growth of organic semiconductors and the charge carrier transport at the interface between the semiconductor and gate insulator. The results indicate that the device performance of low-voltage DNTT OTFTs can be improved by one-pot surface modification of the PEMA gate insulator. (C) 2016 Elsevier B.V. All rights reserved.</P>

Reduction of the Gate Leakage Current in Binary-trench-insulated Gate AlGaN/GaN High-electron-mobility Transistors

김수진,Dong Ho Kim,김재무,정강민,Hong Goo Choi,Cheol-Koo Hahn,김태근 한국물리학회 2009 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.55 No.1

We propose a binary-trench-insulated (BTI) gate structure for reducing the gate leakage current without sacrifice of the transconductance in GaN high-electron-mobility transistors (HEMTs), and its physics-based simulation results are compared with conventional GaN HEMTs and metalinsulator- semiconductor high-electron-mobility-transistors (MIS-HEMTs) with Si3N4 insulators. The gate insulator of AlGaN/GaN BTI-HEMTs consists of two laterally contacting materials with different dielectric constants. The two parallel trench-insulators are composed of oxide and high-k dielectric materials of the same thickness and located within the AlGaN barrier layer. Simulation results clearly indicate that the gate leakage current in the proposed BTI-HEMT is significantly decreased by about two and six orders of magnitude compared to that of the conventional HEMT and MIS-HEMTs. In addition, we observe approximately 57.7% and 15.6% improvements in the maximum drain current density (ID,max) and 40.8% and 65.4% improvements in the maximum transconductance (gm,max) at zero gate bias condition, respectively, as compared to those of the conventional-HEMTs and MIS-HEMTs.

Polymide와 Polyacryl을 게이트 절연층으로 이용한 pentacene TFT의 제작과 전기적 특성에 관한 연구

김윤명,김옥병,김영관,김정수,Kim, Yun-Myoung,Kim, Ok-Byoung,Kim, Young-Kwan,Kim, Jung-Soo 대한전기학회 2001 전기학회논문지C Vol.50 No.4

Organic thin film transitors(TFTs) are of interest for use in broad area electronic applications. For example, in active matrix liquid crystal displays(AMLCDs), organic TFTs would allow the use of inexpensive, light-weight, flexible, and mechanically rugged plastic substrates as an alternative to the glass substrates needed for commonly used hydrogenated amorphous silicon(a-Si:H). Recently pentacene TFTs with carrier field effect, mobility as large as 2 $cm^2V^{-1}s^{-1}$ have been reported for TFTs fabricated on silicon substrates, and it is higher than that of a-Si:H. But these TFTs are fabricated on silicon wafer and $SiO_2$ was used as a gate insulator. $SiO_2$ deposition process requires a high insulator which is polyimide and photo acryl. We investigated trasfer and output characteristics of the thin film transistors having active layer of pentacene. We calculated field effect mobility and on/off ratio from transfer characteristics of pentacene thin film transistor, and measured IR absorption spectrum of polymide used as the gate dielectric layer. It was found that using the photo acryl as a gate insulator, threshold voltage decreased from -12.5 V to -7 V, field effect mobility increased from 0.012 $cm^2V^{-1}s^{-1}$ to 0.039 $cm^2V^{-1}s^{-1}$ , and on/off current ratio increased from $10^5\;to\;10^6$. It seems that TFTs using photo acryl gate insulator is apt to form channel than TFTs using polyimide gate insulator.

Short Channel Analytical Model for High Electron Mobility Transistor to Obtain Higher Cut-Off Frequency Maintaining the Reliability of the Device

Gupta, Ritesh,Aggarwal, Sandeep Kumar,Gupta, Mridula,Gupta, R.S. The Institute of Electronics and Information Engin 2007 Journal of semiconductor technology and science Vol.7 No.2

A comprehensive short channel analytical model has been proposed for High Electron Mobility Transistor (HEMT) to obtain higher cut-off frequency maintaining the reliability of the device. The model has been proposed to consider generalized doping variation in the directions perpendicular to and along the channel. The effect of field plates and different gate-insulator geometry (T-gate, etc) have been considered by dividing the area between gate and the high band gap semiconductor into different regions along the channel having different insulator and metal combinations of different thicknesses and work function with the possibility that metal is in direct contact with the high band gap semiconductor. The variation obtained by gate-insulator geometry and field plates in the field and channel potential can be produced by varying doping concentration, metal work-function and gate-stack structures along the channel. The results so obtained for normal device structure have been compared with previous proposed model and numerical method (finite difference method) to prove the validity of the model.

600 V급 IGBT Single N+ Emitter Trench Gate 구조에 따른 전기적 특성

신명철,육진경,강이구,Shin, Myeong Cheol,Yuek, Jinkeoung,Kang, Ey Goo 한국전기전자재료학회 2019 전기전자재료학회논문지 Vol.32 No.5

In this paper, a single N+ emitter trench gate-type insulated gate bipolar transistor (IGBT) device was studied using T-CAD, in order to achieve a low on-state voltage drop (Vce-sat) and high breakdown voltage, which would reduce power loss and device reliability. Using the simulation, the threshold voltage, breakdown voltage, and on-state voltage drop were studied as a function of the temperature, the length of time in the diffusion process (drive-in) after implant, and the trench gate depth. During the drive-in process, a $20^{\circ}C$ change in temperature from 1,000 to $1,160^{\circ}C$ over a 150 minute time frame resulted in a 1 to 4 V change in the threshold voltage and a 24 to 2.6 V change in the on-state voltage drop. As a result, a 0.5 um change in the trench depth of 3.5 to 7.5 um resulted in the breakdown voltage decreasing from 802 to 692 V.

Enhanced gate-bias stress stability of organic field-effect transistors by introducing a fluorinated polymer in semiconductor/insulator ternary blends

Jeong, Yong Jin,Yun, Dong-Jin,Nam, Sooji,Jang, Jaeyoung Elsevier 2019 APPLIED SURFACE SCIENCE - Vol.481 No.-

<P><B>Abstract</B></P> <P>Solution-processed polymer semiconductors are key materials in the fabrication of lightweight, low-cost, and flexible electronic devices without using the high-vacuum process. For practical applications, reliable device operations based on these materials are required. In this study, we propose a strategy to improve the operation stability of organic field-effect transistors (OFETs) using solution-processed polymer semiconductor/insulator blends as the active channel prepared by introducing a fluorinated insulating polymer in the blends. The semiconducting polymer forms nanowire networks in spin-coated ternary blend films, which serve as charge transport pathways in the insulating polymer matrix consisting of the fluorinated polymer and polystyrene. Owing to its high surface potential attributed to the strongly electron-withdrawing structure, the fluorinated polymer provides a large energy barrier for suppression of the hole trapping at the semiconductor/insulator interface. Consequently, OFETs based on the ternary blend films with an optimized polymer composition exhibit almost hysteresis-free transfer and output characteristics and superior electrical stabilities under sustained gate-bias stresses in both N<SUB>2</SUB> and air atmospheres. We believe that our study provides a practical route to the fabrication of OFETs based on polymer semiconductor/insulator blend systems with high operation stabilities.</P> <P><B>Highlights</B></P> <P> <UL> <LI> A fluorinated polymer PFS was introduced in semiconductor/insulator ternary blends. </LI> <LI> P3HT formed nanowire networks in the blend films and acted as charge transport pathways. </LI> <LI> PFS induced a large energy barrier for suppression of the hole trapping at interfaces. </LI> <LI> The OFETs using the blend film as the active layer exhibited superior gate-bias stabilities. </LI> </UL> </P> <P><B>Graphical abstract</B></P> <P>[DISPLAY OMISSION]</P>