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수소감지를 위한 고감도의 금속 나노선 센서에 관한 연구
안호명,서영호,양원재,김병철,An, Ho-Myoung,Seo, Young-Ho,Yang, Won-Jae,Kim, Byungcheul 한국정보통신학회 2014 한국정보통신학회논문지 Vol.18 No.9
본 연구에서는 팔라듐 (Pd) 나노선으로 구성된 센서의 고감도 수소검지능력에 대해서 조사하였다. 팔라듐 나노선은 알루미늄 양극 산화막 (AAO : anodic aluminum oxide) 채널에 전기도금법을 이용하여 성장시켰으며, 수산화나트륨 수용액을 이용하여 나노선을 분리한 후 포토 리소그래피와 전자빔 리소그래피 공정 및 리프트오프 공정을 사용하여 금속나노선 수소센서를 제작하였다. 2%의 수소에서는 1.92% 의 민감도가, 0.1% 의 수소에서는 0.18% 의 민감도가 변하는 고감도 특성을 얻었으며, 이는 팔라듐 나노선의 저항은 수소의 흡착과 탈착에 의존하기 때문이다. 따라서 상온에서 고감도 수소 가스 검출을 위하여 팔라듐 나노선이 응용될 수 있을 것으로 기대한다. In this paper, we report on an investigation of highly sensitive sensing performance of a hydrogen sensor composed of palladium (Pd) nanowires. The Pd nanowires have been grown by electrodeposition into nanochannels and liberated from the anodic aluminum oxide (AAO) template by dissolving in an aqueous solution of NaOH. A combination of photo-lithography, electron beam lithography and a lift-off process has been utilized to fabricate the sensor using the Pd nanowire. The hydrogen concentrations for 2% and 0.1% were obtained from the sensitivities (${\Delta}R/R$) for 1.92% and 0.18%, respectively. The resistance of the Pd nanowires depends on absorption and desorption of hydrogen. Therefore, we expect that the Pd nanowires can be applicable for detecting highly sensitive hydrogen gas at room temperature.
Low-Temperature Poly-Si TFT Charge Trap Flash Memory with Sputtered ONO and Schottky Junctions
안호명,김주연 한국전기전자재료학회 2015 Transactions on Electrical and Electronic Material Vol.16 No.4
A charge-trap flash (CTF) thin film transistor (TFT) memory is proposed at a low-temperature process (≤ 450℃). The memory cell consists of a sputtered oxide-nitride-oxide (ONO) gate dielectric and Schottky barrier (SB) source/drain (S/D) junctions using nickel silicide. These components enable the ultra-low-temperature process to be successfully achieved with the ONO gate stacks that have a substrate temperature of room temperature and S/D junctions that have an annealing temperature of 200℃. The silicidation process was optimized by measuring the electrical characteristics of the Ni-silicided Schottky diodes. As a result, the Ion/Ioff current ratio is about 1.4×105 and the subthreshold swing and field effect mobility are 0.42 V/dec and 14 cm2/V·s at a drain voltage of -1 V, respectively.
안호명(Ho-Myoung An),이주성(Juseong Lee),김병철(Byungcheul Kim) 한국정보전자통신기술학회 2018 한국정보전자통신기술학회논문지 Vol.11 No.5
본 논문은 140W 급 저면적 LED 전원 제어 회로 설계를 위해 다양한 기능이 집적된 HIC를 제안한다. 제안된 HIC는 정전압/정전류 구동회로, 단락 보호회로, 내부 정전압회로, dimmer 회로를 하나로 집적해, 제작 시 기존 시스템 대비 PCB 가로 길이를 16% 절감하는 효과를 보였다. 다양한 실험을 통해 HIC 내부에 설계된 각 블록의 성능을 검증했고, (정전압 구동회로 변동률 2.9%, dimmer 회로 오차 5%이내, 720 mA에서 안정적인 short protection) 제안된 HIC를 적용해 시스템에서 필요로 하는 전력 대비 PCB 면적을 상당히 줄일 수 있기 때문에, 제작 시간의 대부분을 차지하는 PCB 제조시간을 단출할 수 있는 효과와 전원 제어 회로에서 발생하는 불량에 대해 기존과 같이 PCB 전체를 교체하지 않고 HIC만 교체할 수 있도록 하여 유지/보수를 쉽게 할 수 있는 효과를 기대한다. In this paper, HIC with various functions is proposed for the design 140W LED power control circuit. The proposed HIC integrates constant voltage/constant current circuit, short circuit protection circuit, internal constant voltage circuit, and dimmer circuit, thereby reducing the horizontal length of the PCB by 16% comparing with the conventional system. Through various experiments, we verified the performance of each block implemented inside of HIC with numerical results. (Constant voltage variation ratio: 2.9%, dimmer circuit duty variation within 5%, stable short protection at 720 mA) Since the PCB area can be significantly reduced by applying the proposed HIC. It is possible to reduce the PCB manufacturing time which takes up most of the manufacturing time, however, It is expected that the faulted power module can be replaced without replacing the whole PCB, so that maintenance / repair can be made easier.
남동우,안호명,한태현,이상은,서광열 한국전기전자재료학회 2002 전기전자재료학회논문지 Vol.15 No.7
Nonvolatile semiconductor memory devices with reoxidized nitrided oxide(RONO) gate dielectrics were fabricated, and nitrogen distribution and bonding species which contribute to memory characteristics were analyzed. Also, memory characteristics of devices depending on the anneal temperatures were investigated. The devices were fabricated by retrograde twin well CMOS processes with $0.35\mu m$ design rule. The processes could be simple by in-situ process in growing dielectric. The nitrogen distribution and bonding states of gate dielectrics were investigated by Dynamic Secondary Ion Mass Spectrometry(D-SIMS), Time-of-Flight Secondary Ion Mass Spectrometry(ToF-SIMS), and X-ray Photoelectron Spectroscopy(XPS). As the nitridation temperature increased, nitrogen concentration increased linearly, and more time was required to form the same reoxidized layer thickness. ToF-SIMS results showed that SiON species were detected at the initial oxide interface which had formed after NO annealing and $Si_2NO$ species within the reoxidized layer formed after reoxidation. As the anneal temperatures increased, the device showed worse retention and degradation properties. It could be said that nitrogen concentration near initial interface is limited to a certain quantity, so the excess nitrogen is redistributed within reoxidized layer and contribute to electron trap generation.
CSL-NOR형 SONOS 플래시 메모리의 멀티비트 적용에 관한 연구
김주연,안호명,이명식,김병철,서광열,Kim Joo-Yeon,An Ho-Myoung,Lee Myung-Shik,Kim Byung-Cheul,Seo Kwang-Yell 한국전기전자재료학회 2005 전기전자재료학회논문지 Vol.18 No.3
NOR type flash 32 ${\times}$ 32 way are fabricated by using the typical 0.35 ${\mu}{\textrm}{m}$ CMOS process. The structure of array is the NOR type with common source line. In this paper, optimized program and erase voltage conditions are presented to realize multi-bit per cell at the CSL-NOR array. These are considered selectivity of selected bit and disturbances of unselected bits. Retention characteristics of locally trapped-charges in the nitride layer are investigated. The lateral diffusion and vertical detrapping to the tunneling oxide of locally trapped charges as a function of retention time are investigated by using the charge pumping method. The results are directly shown by change of the trapped-charges quantities.
Interface Traps Analysis as Bonding of The Silicon/Nitrogen/Hydrogen in MONOS Capacitors
김희동,안호명,서유정,장영걸,남기현,정홍배,김태근,Kim, Hee-Dong,An, Ho-Myoung,Seo, Yu-Jeong,Zhang, Yong-Jie,Nam, Ki-Hyun,Chung, Hong-Bay,Kim, Tae-Geun The Institute of Electronics and Information Engin 2009 電子工學會論文誌-CI (Computer and Information) Vol.46 No.12
본 연구는 실리콘 기판과 실리콘 산화막 사이의 계면 트랩 밀도와 게이트 누설 전류를 조사하여, Metal-Oxide-Nitride-Oxide-Silicon (MONOS) 메모리 소자의 계면 트랩 특성의 수소-질소 열처리 효과를 조사하였다. 고속열처리 방법으로 850도에서 30초 동안 열처리한 MONOS 샘플들을 질소 가스와 수소-질소 혼합 가스를 사용하여 450도에서 30분 동안추가 퍼니스 열처리 공정을 수행하였다. 열처리 하지 않은 것, 질소, 수소-질소로 열처리 한 세 개의 샘플 중에서, 커패시터-전압 측정 결과로부터 수소-질소 열처리 샘플들이 가장 적은 계면 트랩 밀도를 갖는 것을 확인하였다. 또한, 전류-전압 측정 결과에서, 수소-질소 열처리 소자의 누설전류 특성이 개선되었다. 위의 실험 결과로부터, 수소-질소 혼합 가스로 추가 퍼니스 열처리의해 실리콘 기판과 산화막 사이의 계면 트랩 밀도를 상당히 줄일 수 있었다. The effect of hydrogen-nitrogen annealing on the interface trap properties of Metal-Oxide-Nitride-Oxide-Silicon (MONOS) capacitors is investigated by analyzing the capacitors' gate leakage current and the interface trap density between the Si and $SiO_2$ layer. MONOS samples annealed at $850^{\circ}C$ for 30 s by rapid thermal annealing (RTA) are treated by additional annealing in a furnace, using annealing eases $N_2$ and 2% hydrogen and 98% nitrogen gas mixture $(N_2-H_2)$ at $450^{\circ}C$ for 30 mins. Among the three samples as-deposited, annealed in $N_2$ and $N_2-H_2$, MONOS sample annealed in an $N_2-H_2$ environment is found to have the lowest increase of interface-trap density from the capacitance-voltage experiments. The leakage current of sample annealed in $N_2-H_2$ is also lower than that of sample annealed in $N_2$.