Lithium ion Implantation에 의한 Silicon p-n Junction 의 Photovoltaic에 관한 硏究

徐光烈 光云大學校 1974 論文集 Vol.3 No.-

Using a 40 KeV acceleration p-type si wafers were doped with Li?ions to form p-?junction and photovoltaic effect studied for various wavelength in an artificial light, Also for each diode an I-V curve was obtained and its relation to the photovoltaic effects studied.

고집적 기억 소자를 위한 초박막 ONO 구조의 특성에 관한 연구

이성배,서광열 광운대학교 신기술연구소 1997 신기술연구소논문집 Vol.26 No.-

본 논문에서 저전압 비휘발성 반도체 기억소자(NVSM)를 위한 scaled ONO(oxide-nitride-oxide)구조의 박막조성과 특성을 조사하였다. 이를 위해 터널링 산화막 20Å질화막 46Å블로킹 산화막 40Å 초박막 ONO 구조의 커패시터형 scaled MONOS 기억소자를 제작하였다. 제작된 ONO 유전막의 조성과 결합 상태는 Auger 분석으로 조사하였으며, 이로부터 scaled ONO 구조에서 블로킹 산화막 성장시 상당량의 O가 질화막 내로 확산하여 질화막이 oxynitride와 같은 특성을 갖게됨을 알 수 있었다. C-V 방법을 이용하여 스위칭 특성을 조사한 결과 6V, 20msec. 의 프로그래밍 조건에서 소자를 소거 상태에서 기록 상태로 스위칭할 수 있었으며, scale-down에도 불구하고 △V_FB,max=4.56V의 최대 평탄밴드 전압 이동량을 얻었다. scaled ONO 구조에서 블로킹 산화막-질화막 계면 트랩의 기억특성에 대한 기여는 90% 이상이었다. 최적 일치 방법으로 구한 질화막 벌크트랩과 블로킹 산화막-질화막 계면 트랩의 밀도는 각각 N_T=7.4×10^l8cm^-3, N_ON=2.3×10^13cm^-2이었다. This paper examines the composition and characteristics of scaled ONO superthin film for future low voltage NVSM applications. Capacitor type MONOS devices with superthin film of 20Åunneling oxide, 46Åitride and 40Ålocking oxide were fabricated. The condition and composition of each layer in ONO dielectrics have been analyzed by Auger depth profile. It is shown in the scaled ONO structure that oxygen is diffused through the thin nitride and oxidized the nitride bulk to form an oxynitride-like layer. High frequency C-V method have been utilized to investigate the switching characteristics. The device can be switched from erased state to a written state by applying a programming voltage of 6V for a programming time of 20msec.In spite of scaling down, the maximum flatband voltage, △V_FB,max=4.56V has been obtained. The scaled nitride layer and nitride-blocking oxide interface permits the storage of charge resulting in adjustable threshold voltages. The contribution of a blocking oxide-nitride interface traps to the memory characteristics is over 90% in a scaled ONO structures. The concentration of nitride bulk traps, N_T=7.4×10^18cm^-3 and blocking oxide-nitride interface traps, N_ON=2.3 ×10^13cm^-2 were determined using the best fitting method.

초박막 ONO 구조의 TDDB 특성

국삼경,서광열 광운대학교 신기술연구소 1998 신기술연구소논문집 Vol.27 No.-

터널링 산화막과 블로킹 산화막의 두께가 각각 23A˚. 40A˚으로 동일하고 질화막이 45A˚, 91A˚, 223A˚으로 서로 다른 캐패시터형의 MONOS(metal-oxide-nitride-oxide-semiconductor) NVSM을 제작한 후, 경사전압 방법과 등전압 방법으로 절연파괴 특성을 측정하여 초박막 ONO 구조의 신뢰성을 조사하였다. 질화막이 23A˚인 초박막 ONO 유전막의 소자가 질화막이 두꺼운 소자에 비해서 우수한 신뢰성을 나타내었다. 따라서 초박막ONO 적층유전막은 MONOS/SONOS 구조를 갖는 비휘발성 반도체 기억소자의 고집적화를 가능하게 함을 알수 있다. Capacitor-trpe MONOS (metal-oxide-nitride-oxide-semiconductor) NVSMs with the same dimensions of the tunneling oxide(23A˚) and blocking oxide(40A˚), but different dimensions of nitride(45A˚. 91A˚ 223A˚) were fabricated. TDDB characteristics of MONOS devices were measured to investigate the reliability of ultrathin ONO structure using ramp voltage and constant voltage method. ultrathin ONO structure with 45A˚ nitride thickness was shown more good reliability than that with 91A˚ and 223A˚ Therefore. ultrathin ONO stacked dielectrics is Promising for scaling of nonvolatile semiconductor memory devices with SONOS/MONOS structure.

과학기술계산을 위한 전자계산기용 특수 Library 개발에 관한 연구

金相萬,姜承業,沈在洪,文東纘,徐光烈,洪勝弘,愼哲宰 광운대학교 1972 論文集 Vol.2 No.-

In this paper the subroutine library of digital computer techniques to the solution of electronic networks problem are discussed. The application of digital-computer techniques to the solution of the integrations relating the terminal variables for linear time invariant inductos and capaciters are analyzed, then on the techniques of numerical integrations trapezoidal method is used. The subroutine library for differential equations and determinations which are used in electronic networks analysis have been developed. Since these programs are the general form, anybody can utilize the programs for his own purpose.

CP 법을 이용한 Short 채널 SONOSFET 비휘발성 기억소자의 Si-SiO2 계면 및 열화특성에 관한 연구

서광열(Kwang Yell Seo) 광운대학교 인문사회과학연구소 1994 인문사회과학논문집 Vol.23 No.-

MNOS 기억소자에서 C-V 분석방법에 의한 계면상태밀도의 에너지 분포

서광열 光云大學校 1991 論文集 Vol.20 No.-

In the nonvolatile MNOS(Metal-Nitride-Oxide-Semoconductor)memory devices with SiO₂layer of 23A thick and Si₃N₄layer of 53OA thick, the energy distribution of the Si- SiO₂interface state density was determined by using different C-V analysis methods. The high frequency C-V curves was measured at a frequency of 1 MHz, and the low frequency C-V curves was obtained from the quasi-static measurement technique. All the measurements were made at a temperature of 300K. The voltage sweep was also limited to ±4V to avoid memory changes. The low frequency and high frequency C-V curves were, respectively, used to establish the relation between the gate valtage and the semiconductor surface potential. The low frequency method was appropriate to investigate the whole range of the energy band gap. The combined low-high frequency capacitance method was valid to investigate only the upper half of the energy band gap. However, as the V? vs. Φ? relation obtained from the low frequency C-V curves was applied to the combined low-high frequency capacitance method. Without the theoretical semiconductor capacitance C?(Φ?), it was possible to investigate exactly the energy distribution of the interface state density through the whole range of the energy band gap with only the measured C-V curves. As a result, the Si- SiO₂ interface states were distributed over all the energy band gap with the density of 10?~10?eV??cm?.

MNOS 다이오드의 Memory Trap에 관한 연구

서광열 光云大學校 1985 論文集 Vol.14 No.-

In this paper, we are examined, trap states and discharging mechanism of metal-nitride-oxide- semiconductor devices using C-V measurement and TSC technique. One of the four TSC components which is due to traps in nitride and oxide-nitride inter-face and known to contribute memory effect can be separated from other components and examined. Charges released from memory trap are measured in TSC and compared with the charge calculated from the flat band voltage shift before and after TSC measurement. It is observed good correlation between Q(TSC) and Q(ΔVFB). Peak shape method and heating rate method are applied to determine the trap energy level. As the results, the energy level of the memory trap lies 0.44-0.66eV from the bottom of nitride conduction band and frequency factor is 6.58×10( )sec( )

CP법을 이용한 Short 채널 SONOSFET 비휘발성 기억소자의 Si-SiO₂계면 및 열화특성에 관한 연구

서광열 光云大學校 1994 論文集 Vol.23 No.-

The characteristics of the Si-SiO? interface and the Degradation in the short channel(L×W=1.7㎛×1.5㎛) SONOSFET nonvolatile memory devices, fabricated on the basis of the existing n-well CMOS processing technology for 1 Mbit DRAM with the 1.2㎛ design rule, were investigated using the charge pumping method. The SONOSFET memories have the tripple insulated-gate consisting of 30A tunneling oxide, 205A nitride and 65A blocking oxide. In order to examine a larger part of the forbidden band, the charge pumping currents were measured at different temperatures in the range of 80K∼350K. The acceleration method, which square voltage pulses of t?=10msec, V?=+19V and V?=-22V continue to be alternatly applied to gate, was used to investigate the degradation of SONOSFET memories with the write/erase cycle. The degradation characteristics were ascertained by observing the change in the interface trap distributions. The experimental results reveal that for 0 cycle, the interface traps were distributed in the upper and lowere half between 0.20eV∼0.52eV from the middle of bandgap, with their densities of 3.1×10??∼7.9×10??cm??eV??, 2/9×10??∼7.8×10??cm??eV??, respectively, and that SONOSFET memories were degraded at 5×10? cycles.

Inhibiting the cytosolic funaction of CXXC5 accelerates diabetic wound healing by enhancing angiogenesis and skin repair

Kim Eunhwan,Seo Seol Hwa,Hwang Yumi,Ryu Yeong Chan,Ryu Yeong Chan,Lee Kyoung-Mi,Lee Jin Woo,Park Kwang Hwan,Choi Kang-Yell 생화학분자생물학회 2023 Experimental and molecular medicine Vol.55 No.-

Diabetic wound healing, including diabetic foot ulcer (DFU), is a serious complication of diabetes. Considering the complexity of DFU development, the identification of a factor that mediates multiple pathogeneses is important for treatment. In this study, we found that CXXC-type zinc finger protein 5 (CXXC5), a negative regulator of the Wnt/β-catenin pathway, was overexpressed with suppression of the Wnt/β-catenin pathway and its target genes involved in wound healing and angiogenesis in the wound tissues of DFU patients and diabetes-induced model mice. KY19334, a small molecule that activates the Wnt/β-catenin pathway by inhibiting the CXXC5-Dvl interaction, accelerated wound healing in diabetic mice. The enhancement of diabetic wound healing could be achieved by restoring the suppressed Wnt/β-catenin signaling and subsequently inducing its target genes. Moreover, KY19334 induced angiogenesis in hindlimb ischemia model mice. Overall, these findings revealed that restorative activation of Wnt/β-catenin signaling by inhibiting the function of cytosolic CXXC5 could be a therapeutic approach for treating DFUs.

Realization of Two-bit Operation by Bulk-biased Programming Technique in SONOS NOR Array with Common Source Lines

An, Ho-Myoung,Seo, Kwang-Yell,Kim, Joo-Yeon,Kim, Byung-Cheul The Korean Institute of Electrical and Electronic 2006 Transactions on Electrical and Electronic Material Vol.7 No.4

We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.