${Cu_6}{Sn_5}$를 분산시켜 스크린 프린팅법으로 제조한 Sn-Pb 솔더범프의 전단강도

최진원,이광응,차호섭,오태성,Choe, Jin-Won,Lee, Gwang-Eung,Cha, Ho-Seop,O, Tae-Seong 한국재료학회 2000 한국재료학회지 Vol.10 No.12

63Sn-37Pb에 Cu$_{6}$Sn$_{5}$를 분산시킨 760$\mu\textrm{m}$크기의 솔더범프를 Au(0.5$\mu\textrm{m}$)/Ni(5$\mu\textrm{m}$)/Cu(27$\pm$20$\mu\textrm{m}$) BGA 기판에 스크린)/Ni(5im)/Cu(27:201m) B3GA 기판에 스크린 프린팅법으로 제조하여, 리플로우 피크온도 유지시간, 15$0^{\circ}C$ 시효처리 시간에 따른 전단강도를 분석하였다. Cu$_{6}$Sn$_{5}$를 첨가한 솔더범프는 피크온도에서 30초간 유지시에는 63Sn-37Pb 솔더범프보다 높은 전단강도를 나타내었으나, 피크온도 유지시간을 60초 이상으로 증가시킴에 따라 전단강도가 63Sn-37Pb 솔더범프보다 저하하였다. 전단시험 후 솔더범프의 파단면은 초기에 전단 균열의 점진적인 전파에 의해 발생된 파괴부위와 점진적 균열전파에 의한 면적 감소로 솔더범프가 급격히 떨어져 나가면서 발생한 파괴부위로 구분할 수 있었다 피크온도 유지시간, 15$0^{\circ}C$ 시효처리 시간 및 Cu$_{6}$Sn$_{5}$ 첨가량에 무관하게 점진적 파괴모드에 의한 균열 전파길이가 증가할수록 솔더범프의 전단강도가 감소하였다.감소하였다. Cu$_{6}$Sn$_{5}$-dispersed 63Sn-37Pb solder bumps of 760$\mu\textrm{m}$ size were fabricated on Au(0.5$\mu\textrm{m}$)/Ni(5$\mu\textrm{m}$)/Cu(27$\pm$20$\mu\textrm{m}$) BGA substrates by screen printing process, and their shear strength were characterized with variations of dwell time at reflow peak temperature and aging time at 15$0^{\circ}C$ . With dwell time of 30 seconds at reflow peak temperature, the solder bumps with Cu$_{6}$Sn$_{5}$ dispersion exhibited higher shear strength than the value of the 63Sn-37Pb solder bump. With increasing the dwell time longer than 60 seconds, however the shear strength of the Cu$_{6}$Sn$_{5}$-dispersed solder bumps became lower than that the 63Sn-37Pb solder bumps. The failure surface of the solder bumps could be divided into two legions of slow crack propagation and critical crack propagation. The shear strength of the solder bumps was inversely proportional to the slow crack propagation length, regardless of the dwell time at peak temperature, aging time at 150 $^{\circ}C$ and the volume fraction of Cu$_{6}$Sn$_{5}$ dispersion.> 5/ dispersion.

플립칩용 Sn-Cu 전해도금 솔더 범프의 형성 연구

정석원,강경인,정재필,주운홍 한국마이크로전자및패키징학회 2003 마이크로전자 및 패키징학회지 Vol.10 No.4

플립칩용으로 Sn-Cu 공정 솔더 범프를 전해도금을 이용하여 제조하고 특성을 연구하였다. Si 웨이퍼 위에 UBM(Under Bump Metallization)으로 Al(400 nm)/Cu(300 nm)/Ni(400 nm)/Au(20 nm)를 전자빔 증착기로 증착하였다. 전류밀도가 1 A/d$\m^2$에서 8 A/d$\m^2$으로 증가함에 따라 Sn-Cu 솔더의 도금속도는 0.25 $\mu\textrm{m}$/min에서 2.7 $\mu\textrm{m}$/min으로 증가하였다. 이 전류밀도의 범위에서 전해도금된 Sn-Cu 도금 합금의 조성은 Sn-0.9∼1.4 wt%Cu의 거의 일정한 상태를 유지하였다. 도금 전류밀도 5 A/d$\m^2$, 도금시간 2hrs, 온도 $20^{\circ}C$의 조건에서 도금하였을 때, 기둥 직경 약 120 $\mu\textrm{m}$인 양호한 버섯 형태의 Sn-Cu 범프를 형성할 수 있었다. 버섯형 도금 범프를 $260^{\circ}C$에서 리플로우 했을 때 직경 약 140 $\mu\textrm{m}$의 구형 범프가 형성되었다. 화학성분의 균일성을 분석한 결과 버섯형 범프에서 존재하던 범프내 Sn 등 성분 원소의 불균일성은 구형 범프에서는 상당 부분 해소 되었다. Sn-Cu eutectic solder bump was fabricated by electroplating for flip chip and its characteristics were studied. A Si-wafer was used as a substrate and the UBM(Under Bump Metallization) of Al(400 nm)/Cu(300 nm)/Ni(400 nm)/Au(20 nm) was coated sequentially from the substrate to the top by an electron beam evaporator. The experimental results showed that the plating ratio of the Sn-Cu increased from 0.25 to 2.7 $\mu\textrm{m}$/min with the current density of 1 to 8 A/d$\m^2$. In this range of current density the plated Sn-Cu maintains its composition nearly constant level as Sn-0.9∼1.4 wt%/Cu. The solder bump of typical mushroom shape with its stem diameter of 120 $\mu\textrm{m}$ was formed through plating at 5 A/d$\m^2$ for 2 hrs. The mushroom bump changed its shape to the spherical type of 140 $\mu\textrm{m}$ diameter by air reflow at $260^{\circ}C$. The homogeneity of chemical composition for the solder bump was examined, and Sn content in the mushroom bump appears to be uneven. However, the Sn distributed more uniformly through an air reflow.

Cu 범프와 Sn 범프의 접속구조를 이용한 RF 패키지용 플립칩 공정

최정열,김민영,임수겸,오태성,Choi, J.Y.,Kim, M.Y.,Lim, S.K.,Oh, T.S. 한국마이크로전자및패키징학회 2009 마이크로전자 및 패키징학회지 Vol.16 No.3

Cu pillar 범프를 사용한 플립칩 접속부는 솔더범프 접속부에 비해 칩과 기판사이의 거리를 감소시키지 않으면서 미세피치 접속이 가능하기 때문에, 특히 기생 캐패시턴스를 억제하기 위해 칩과 기판사이의 큰 거리가 요구되는 RF 패키지에서 유용한 칩 접속공정이다. 본 논문에서는 칩에는 Cu pillar 범프, 기판에는 Sn 범프를 전기도금하고 이들을 플립칩 본딩하여 Cu pillar 범프 접속부를 형성 한 후, Sn 전기도금 범프의 높이에 따른 Cu pillar 범프 접속부의 접속저항과 칩 전단하중을 측정하였다. 전기도금한 Sn 범프의 높이를 5 ${\mu}m$에서 30 ${\mu}m$로 증가시킴에 따라 Cu pillar 범프 접속부의 접속저항이 31.7 $m{\Omega}$에서 13.8 $m{\Omega}$로 향상되었으며, 칩 전단하중이 3.8N에서 6.8N으로 증가하였다. 반면에 접속부의 종횡비는 1.3에서 0.9로 저하하였으며, 접속부의 종횡비, 접속저항 및 칩 전단하중의 변화거동으로부터 Sn 전기도금 범프의 최적 높이는 20 ${\mu}m$로 판단되었다. Compared to the chip-bonding process utilizing solder bumps, flip chip process using Cu pillar bumps can accomplish fine-pitch interconnection without compromising stand-off height. Cu pillar bump technology is one of the most promising chip-mounting process for RF packages where large gap between a chip and a substrate is required in order to suppress the parasitic capacitance. In this study, Cu pillar bumps and Sn bumps were electroplated on a chip and a substrate, respectively, and were flip-chip bonded together. Contact resistance and chip shear force of the Cu pillar bump joints were measured with variation of the electroplated Sn-bump height. With increasing the Sn-bump height from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance was improved from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$ and the chip shear force increased from 3.8 N to 6.8 N. On the contrary, the aspect ratio of the Cu pillar bump joint decreased from 1.3 to 0.9. Based on the variation behaviors of the contact resistance, the chip shear force, and the aspect ratio, the optimum height of the electroplated Sn bump could be thought as 20 ${\mu}m$.

Electromigration Characteristics of Flip Chip Sn-3.5Ag Solder Bumps under Highly Accelerated Conditions

이장희,임기태,양승택,서민석,정관호,변광유,박영배 한국물리학회 2009 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.54 No.5

The effects of severe current crowding and Joule heating on the damage morphology and the electromigration parameters were evaluated for flip chip Sn-3.5Ag solder bumps with Cu under- bump metallurgy. in-situ electromigration testing in a scanning electron microscope was performed to correlate the statistical lifetimes with the detailed microstructural characteristics. The highly accelerated test conditions used led to an activation energy of 1.63 eV and a current density exponent of 4.6, which can be attributed to severe current crowding and Joule heating effects. Real-time microstructural analysis revealed that interfacial voids nucleated around corners of the under-bump metallurgy layer, where electrons entered from the chip or the substrate interconnect line to the solder bump and then grew along the Cu6Sn5/solder interface, irrespective of the current flow's direction. Accelerated growth of Kirkendall voids was also observed at the Cu3Sn/Cu interface and within Cu3Sn. However, electrical failure of the bump resulted from electromigration-induced interfacial void propagation along the Cu6Sn5/solder interface, which can be explained in terms of the large difference in Cu diffusion flux between the Cu-Sn intermetallic compound layer and the solder itself. The effects of severe current crowding and Joule heating on the damage morphology and the electromigration parameters were evaluated for flip chip Sn-3.5Ag solder bumps with Cu under- bump metallurgy. in-situ electromigration testing in a scanning electron microscope was performed to correlate the statistical lifetimes with the detailed microstructural characteristics. The highly accelerated test conditions used led to an activation energy of 1.63 eV and a current density exponent of 4.6, which can be attributed to severe current crowding and Joule heating effects. Real-time microstructural analysis revealed that interfacial voids nucleated around corners of the under-bump metallurgy layer, where electrons entered from the chip or the substrate interconnect line to the solder bump and then grew along the Cu6Sn5/solder interface, irrespective of the current flow's direction. Accelerated growth of Kirkendall voids was also observed at the Cu3Sn/Cu interface and within Cu3Sn. However, electrical failure of the bump resulted from electromigration-induced interfacial void propagation along the Cu6Sn5/solder interface, which can be explained in terms of the large difference in Cu diffusion flux between the Cu-Sn intermetallic compound layer and the solder itself.

비전도성 접착제를 이용한 COG 본딩용 Sn/Ag 범프에서 본딩 응력이 접속저항에 미치는 영향

이광용,이윤희,김영호,오태성 대한금속재료학회 2005 대한금속·재료학회지 Vol.43 No.3

Chip-on-glass bonding using nonconductive adhesive was accomplished with joining of the Sn/Ag bumps, and the average contact resistance of the Sn/Ag bump was measured with variation of the bonding stress. Average contact resistance of the Sn/Ag bump could be obtained from the slope of the curve for daisy chain resistance vs. number of Sn/Ag bumps. With increasing the bonding stress from 31.8 MPa to 69.8 MPa, the average contact resistance decreased from 30 mil/bump to 15.6 mΩ/bump. With further increasing the bonding stress above 69.8 MPa, however, the average contact resistance changed little within the range of 12.9-15.6 mil/bump. Among the factors affecting the contact resistance with variation of the bonding stress, plastic deformation of the Sn/Ag bump had larger effect than the amount of the microvoids remaining at the contact interface between Sn/Ag bumps. (Received November 22, 2004)

3차원 적층 패키지를 위한 Cu/thin Sn/Cu 범프구조의 금속간화합물 성장거동분석

박영배 ( Young Bae Park ),김재원 ( Jae Won Kim ),김병준 ( Byoung Joon Kim ),김재동 ( Jae Dong Kim ),주영창 ( Young Chang Joo ),이기욱 ( Ki Wook Lee ),정명혁 ( Myeong Hyeok Jeong ),곽병현 ( Byung Hyun Kwak ) 대한금속재료학회(구 대한금속학회) 2011 대한금속·재료학회지 Vol.49 No.2

Isothermal annealing and electromigration tests were performed at 125℃ and 125℃, 3.6×104 A/cm2 conditions, respectively, in order to compare the growth kinetics of the intermetallic compound (IMC) in the Cu/thin Sn/Cu bump. Cu6Sn5 and Cu3Sn formed at the Cu/thin Sn/Cu interfaces where most of the Sn phase transformed into the Cu6Sn5 phase. Only a few regions of Sn were not consumed and trapped between the transformed regions. The limited supply of Sn atoms and the continued proliferation of Cu atoms enhanced the formation of the Cu3Sn phase at the Cu pillar/Cu6Sn5 interface. The IMC thickness increased linearly with the square root of annealing time, and increased linearly with the current stressing time, which means that the current stressing accelerated the interfacial reaction. Abrupt changes in the IMC growth velocities at a specific testing time were closely related to the phase transition from Cu6Sn5 to Cu3Sn phases after complete consumption of the remaining Sn phase due to the limited amount of the Sn phase in the Cu/thin Sn/Cu bump, which implies that the relative thickness ratios of Cu and Sn significantly affect Cu-Sn IMC growth kinetics.

Electrodeposition 변수에 따른 Sn 도금의 표면 거칠기와 플립칩 접속된 Sn 범프의 접속저항

정부양,박선희,김영호,오태성,Jung, Boo-Yang,Park, Sun-Hee,Kim, Young-Ho,Oh, Tae-Sung 한국마이크로전자및패키징학회 2006 마이크로전자 및 패키징학회지 Vol.13 No.4

플립칩 공정에 Sn 범프를 적용하기 위해 도금전류밀도와 전류모드에 따른 Sn 도금막의 표면 거칠기와 경도를 측정하였다. 전류밀도 $5{\sim}50\;ma/cm^{2}$에서 전기도금한 Sn 도금막은 $2.0{\sim}2.4{\mu}m$의 표면 거칠기를 나타내었으며, 직류모드보다 펄스모드로 형성한 Sn 도금막에서 표면 거칠기가 감소하였다 할로겐 램프를 사용하여 $300^{\circ}C$에서 3초간 유지하는 표면 열처리에 의해 Sn 도금의 표면 거칠기가 $1\;{\mu}m$ 정도로 현저히 저하되었다. 전류밀도 $5{\sim}50mA/cm^{2}$에서 전기도금한 Sn 도금막은 10 Hv의 경도를 나타내었다. Sn 범프들을 이용하여 플립칩 본딩한 시편들은 $33{\sim}17m{\Omega}$의 낮은 접속저항을 나타내었다. Surface roughness and hardness of the electroplated Sn were characterized with variations of electroplating current density and current mode. The Sn electroplated at $5{\sim}50mA/cm^{2}$ exhibited the surface roughness of $2.0{\sim}2.4{\mu}m$. The Sn electroplated with pulse current mode exhibited low surface roughness compared one processed with direct current mode. With surface annealing at $300^{\circ}C$ for 3 sec using halogen lamp, surface roughness of the Sn bump was substantially reduced to $1{\mu}m$. The Sn electroplated at $5{\sim}50mA/cm^{2}$ exhibited the hardness of 10 Hv. Low contact resistances of $33{\sim}17m{\Omega}$ were obtained for specimens flip-chip bonded with Sn bumps.

무전해 도금법을 이용한 Sn-Cu 범프 형성에 관한 연구

문윤성,이재호,Moon, Yun-Sung,Lee, Jae-Ho 한국마이크로전자및패키징학회 2008 마이크로전자 및 패키징학회지 Vol.15 No.2

Sn-Cu계 솔더 범프에서 무전해도금법을 이용한 범프 형성에 대한 연구를 하였다. $20{\mu}m$ via에 전기도금법으로 구리를 채운 웨이퍼 위에 ball형태의 범프를 형성하기 위하여 구리와 주석을 도금하여 약 $10{\mu}m$높이의 범프를 형성하였다. 구리 범프 형성 시 via위에 선택적으로 도금하기 위하여 활성화 처리 후 산세처리를 실시하고 무전해 도금액에 안정제를 첨가하였다. 무전해도금법을 이용하여 주석 범프 형성 시 도금층이 구리 범프에 비해 표면의 균일도가 벌어지는 것으로 관찰되었지만 reflow공정을 실시한 후 ball 형태의 균일한 Sn-Cu 범프를 형성하였다. The electroless plating of copper and tin were investigated for the fabrication of Sn-Cu bump. Copper and tin were electroless plated in series on $20{\mu}m$ diameter copper via to form approximately $10{\mu}m$ height bump. In electroless copper plating, acid cleaning and stabilizer addition promoted the selectivity of bath on the copper via. In electroless tin plating, the coating thickness of tin was less uniform relative to that of electroless copper, however the size of Sn-Cu bump were uniform after reflow process.

The Stability of Plating Solution and the Current Density Characteristics of the Sn-Ag Plating for the Wafer Bumping

Dong-Hyun Kim,Seong-Jun Lee 한국표면공학회 2017 한국표면공학회지 Vol.50 No.3

In this study, the effects of the concentration of metal ions and the applied current density in the Sn-Ag plating solutions were examined in regards to the resulting composition and morphology of the solder bumps’ surface. Furthermore the effect of any impurities present in the methanesulfonic acid used as a base acid in the Sn-Ag solder plating solution on the stability of plating solution as well as the characteristics of the Sn-Ag alloys films was also explored. As expected, the uniform bump was obtained by means of removing impurities in the plating solution. Consequently the resultant solder bump was obtained in an optimal current density of the range of 1 A/dm<SUP>2</SUP> to 15 A/dm<SUP>2</SUP>, which has acceptable bump shape and surface roughness with 12inch wafer trial results.

플렉서블 기반 미세 무연솔더 범프를 이용한 칩 접합 공정 기술

김민수,고용호,방정환,이창우,Kim, Min-Su,Ko, Yong-Ho,Bang, Jung-Hwan,Lee, Chang-Woo 한국마이크로전자및패키징학회 2012 마이크로전자 및 패키징학회지 Vol.19 No.3

In electronics industry, the coming electronic devices will be expected to be high integration and convergence electronics. And also, it will be expected that the coming electronics will be flexible, bendable and wearable electronics. Therefore, the demands and interests of bonding technology between flexible substrate and chip for mobile electronics, e-paper etc. have been increased because of weight and flexibility of flexible substrate. Considering fine pitch for high density and thermal damage of flexible substrate during bonding process, the micro solder bump technology for high density and low temperature bonding process for reducing thermal damage will be required. In this study, we researched on bonding technology of chip and flexible substrate by using 25um Cu pillar bumps and Sn-Bi solder bumps were formed by electroplating. From the our study, we suggest technology on Cu pillar bump formation, Sn-Bi solder bump formation, and bonding process of chip and flexible substrate for the coming electronics.