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Kim Ye-Seul,Choi Jae-Woong,Song Sang Hoon,Hwang Ho Young,Sohn Suk Ho,Kim Ji Seong,Kang Yoonjin,Gu Ja-Yoon,Kim Kyung-Hwan,Kim Hyun Kyung 대한진단검사의학회 2023 Annals of Laboratory Medicine Vol.43 No.4
Background: Point-of-care testing (POCT) coagulometers are increasingly used for monitoring warfarin therapy. However, in high international normalized ratio (INR) ranges, significant discrepancy in the INR between POCT and conventional laboratory tests occurs. We compared the INR of POCT (CoaguChek XS Plus; Roche Diagnostics, Mannheim, Germany) with that of a conventional laboratory test (ACL TOP 750; Instrumentation Laboratory SpA, Milan, Italy) and explored possible reasons for discrepancy. Methods: Paired POCT and conventional laboratory test INRs were analyzed in 400 samples from 126 patients undergoing warfarin therapy after cardiac surgery. Coagulation factor and thrombin generation tests were compared using the Mann–Whitney U test. Correlations between coagulation factors and INRs were determined using Pearson correlation coefficients. Results: The mean difference in the INR between the tests increased at high INR ranges. Endogenous thrombin potential levels were decreased at INR <2.0 for CoaguChek XS Plus and 2.0< INR <3.0 for ACL TOP 750 compared with those at INR <2.0 for both tests, indicating a better performance of ACL TOP 750 in assessing thrombin changes. The correlation coefficients of coagulation factors were stronger for ACL TOP 750 INR than for CoaguChek XS Plus INR. Vitamin K-dependent coagulation factors were found to contribute to the INR discrepancy. Conclusions: Decreases in vitamin K-dependent coagulation and anticoagulation factors can explain the significant discrepancy between the two tests in high INR ranges. Since conventional laboratory test INR values are more reliable than POCT INR values, a confirmatory conventional laboratory test is required for high INR ranges.
Efficient Fault-Recovery Technique for CGRA-based Multi-Core Architecture
Yoonjin Kim,Seungyeon Sohn 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.2
In this paper, we propose an efficient faultrecovery technique for CGRA (Coarse-Grained Reconfigurable Architecture) based multi-core architecture. The proposed technique is intra/inter-CGRA co-reconfiguration technique based on a ringbased sharing fabric (RSF) and it enables exploiting the inherent redundancy and reconfigurability of the multi-CGRA for fault-recovery. Experimental results show that the proposed approaches achieve up to 73% fault recoverability when compared with completely connected fabric (CCF).
Dynamic Redundancy-based Fault-Recovery Scheme for Reliable CGRA-based Multi-Core Architecture
Yoonjin Kim,Seungyeon Sohn 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.6
CGRA (Coarse-Grained Reconfigurable Architecture) based multi-core architecture can be considered as a suitable solution for the fault-tolerant computing. However, there have been a few research projects based on fault-tolerant CGRA without exploiting the strengths of CGRA as well as their works are limited to single CGRA. Therefore, in this paper, we propose two approaches to enable exploiting the inherent redundancy and reconfigurability of the multi-CGRA for faultrecovery. One is a resilient inter-CGRA fabric that is ring-based sharing fabric (RSF) with minimal interconnection overhead. Another is a novel intra/inter-CGRA reconfiguration technique on RSF for maximizing utilization of the resources when faults occur. Experimental results show that the proposed approaches achieve up to 94% faulty recoverability with reducing area/delay/power by up to 15%/28.6%/31% when compared with completely connected fabric (CCF).
Kim, Min Joo,Kim, TaeYeong,Choi, Yoonjin,Oh, Sejun,Kim, Kabsu,Yoon, BumChul Elsevier 2016 EUROPEAN JOURNAL OF INTEGRATIVE MEDICINE Vol.8 No.5
<P><B>Abstract</B></P> <P><B>Introduction</B></P> <P>Energy expenditure, enjoyment, and task difficulty were compared for exercise with a horse riding simulator (HRS) and real horseback riding (RHR), and analyzed according to riding speed and participant age.</P> <P><B>Methods</B></P> <P>The HRS and RHR groups comprised 19 and 18 young adults and 21 and 10 elderly subjects, respectively. A visual analog scale was used to measure perceived enjoyment and task difficulty, and pulmonary gas exchange was used to calculate oxygen uptake and metabolic equivalents (METs). Participants either rode the simulator on a treadmill or a real horse on a treadmill at various speeds for 15min.</P> <P><B>Results</B></P> <P>Participants reported greater enjoyment from riding a real horse. There were no significant differences between groups in task difficulty, oxygen uptake, or METs. When the speed increased, the gait pattern elicited faster and more complex coordination, and significantly improved energy expenditure, enjoyment, and task difficulty. The elderly showed greater enjoyment and less task difficulty than young adults.</P> <P><B>Conclusions</B></P> <P>HRS and RHR provide low-level exercise intensity. The elderly reported greater enjoyment and less task difficulty than young adults for both HRS and RHR exercise. These results indicate that HRS might be a feasible substitute for RHR for the elderly, with comparable exercise effects at low intensity. Low-intensity exercise provided by HRS could also be a safe and appealing intervention for the elderly.</P>
Efficient Reconfigurable Architecture to Accelerate Descriptor Extraction in SURF Algorithm
Kim, Yoonjin,Jung, Haelim The Institute of Electronics and Information Engin 2018 Journal of semiconductor technology and science Vol.18 No.3
Speeded-up robust features (SURF) is considered to be the most efficient feature extraction algorithm and it has been implemented in powerful hardware for real-time operation due to its characteristics of data-intensive computation of high complexity. Especially the computational load of the descriptor extraction procedure is very significant and the overall performance of SURF can be improved by speeding up the descriptor extraction step with increasing parallel hardware accelerators. However, simply increasing the hardware accelerators is burdensome because of causing significant area and power consumption. Therefore, in this paper, we propose a reconfigurable hardware architecture that enables achieving the maximum performance of the descriptor extraction step with making the best use of the existing accelerators without any additional ones. Experimental results show that the proposed architecture improves the performance of the descriptor extraction step by 21.51% ~ 47.31% with negligible area and small power overheads of less than 1% and 4% when compared with the existing hardware implementations of the SURF algorithm.
Reconfigurable Multi-Array Architecture for LowPower and High-Speed Embedded Systems
Yoonjin Kim 대한전자공학회 2011 Journal of semiconductor technology and science Vol.11 No.3
Coarse-grained reconfigurable architecture (CGRA) based embedded systems aims to achieve high system performance with sufficient flexibility to map a variety of applications. However, the CGRA has been considered as prohibitive one due to its significant area/power overhead and performance bottleneck. In this work, I propose reconfigurable multi-array architecture to reduce power/area and enhance performance in configurable embedded systems. The CGRA-based embedded systems that consist of hierarchical configurable computing arrays with varying size and communication speed were examined for multimedia and other applications. Experimental results show that the proposed approach reduces on-chip area by 22%, execution time by up to 72% and reduces power consumption by up to 55% when compared with the conventional CGRA-based architectures.