1 "http://www.netlib.org/benchmark/livermorec"
2 "http://www.ert.de/Projekte/Tools/DSPSTONE"
3 Reiner Hartenstein, "decade of reconfigurable computing: a visionary retrospective" 642-649, 2001
4 Timothy J. Callahan, "The Garp architecture and C compiler" 33 (33): 62-69, 2000
5 Jonghee W. Yoon, "Temporal Mapping for Loop Pipelining on a MIMD style Coarse-Grained Reconfigurable Architecture" 2006
6 Michalis D. Galanis, "Speedups in embed-ded systems with a high-performance coprocessor datapath" 12 (12): 2007
7 김윤진, "Resource sharing and pipelining in coarse-grained reconfigurable architecture for domain-specific optimization" IEEE Computer Society/ACM SIGDA 12-17, 2005
8 Hartej Singh, "MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applica-tions" 49 (49): 465-481, 2000
9 Jong-eun Lee, "Mapping loops on coarsegrained reconfigurable architectures using memory operation sharing" Center for Embedded Computer Sys-tems(CECS), Univ. of California Irvine, Calif. 2002
10 C. Arbelo, "Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: the H.264/AVC deblock-ing filter" 642-649, 2007
1 "http://www.netlib.org/benchmark/livermorec"
2 "http://www.ert.de/Projekte/Tools/DSPSTONE"
3 Reiner Hartenstein, "decade of reconfigurable computing: a visionary retrospective" 642-649, 2001
4 Timothy J. Callahan, "The Garp architecture and C compiler" 33 (33): 62-69, 2000
5 Jonghee W. Yoon, "Temporal Mapping for Loop Pipelining on a MIMD style Coarse-Grained Reconfigurable Architecture" 2006
6 Michalis D. Galanis, "Speedups in embed-ded systems with a high-performance coprocessor datapath" 12 (12): 2007
7 김윤진, "Resource sharing and pipelining in coarse-grained reconfigurable architecture for domain-specific optimization" IEEE Computer Society/ACM SIGDA 12-17, 2005
8 Hartej Singh, "MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applica-tions" 49 (49): 465-481, 2000
9 Jong-eun Lee, "Mapping loops on coarsegrained reconfigurable architectures using memory operation sharing" Center for Embedded Computer Sys-tems(CECS), Univ. of California Irvine, Calif. 2002
10 C. Arbelo, "Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: the H.264/AVC deblock-ing filter" 642-649, 2007
11 Huesung Kim, "Low-power high-performance reconfigurable computing cache architectures" 53 (53): 1274-1290, 2004
12 Francisco Barat, "Low power coarse-grained reconfigurable instruction set processor" 230-239, 2003
13 "Gaisler Research"
14 A. Deledda, "Design of a HW/SW communication infra-structure for a heterogeneous reconfigurable processor" 1352-1357, 2008
15 Marco Lanuzza, "Cost-effective low-power processor-in-memory-based reconfig' datapath for multimedia applications" 161-166, 2005
16 A. S. Y. Poon, "An Energy-Efficient Reconfigurable Baseband Processor for Wireless Communications" 15 (15): 319-327, 2007
17 T. Miyamori, "A quantitative analysis of reconfigurable coprocessors for multimedia appli-cations" 15-17, 1998