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Strained SGOI n-MOSFET에서의 phonon-limited전자이동도의 Si두께 의존성
심태헌,박재근,Shim Tae-Hun,Park Jea-Gun 대한전자공학회 2005 電子工學會論文誌-SD (Semiconductor and devices) Vol.42 No.9
60 nm C-MOSFET 기술 분기점 이상의 고성능, 저전력 트랜지스터를 구현 시키기 위해 SiGe/SiO2/Si위에 성장된 strained Si의 두께가 전자 이동도에 미치는 영향을 두 가지 관점에서 조사 연구하였다. 첫째, inter-valley phonon 산란 모델의 매개변수들을 최적화하였고 둘째, strained Si 반전층의 2-fold와 4-fold의 전자상태, 에너지 밴드 다이어그램, 전자 점유도, 전자농도, phonon 산란율과 phonon-limited 전자이동도를 이론적으로 계산하였다. SGOI n-MOSFET의 전자이동도는 고찰된 SOI 구조의 Si 두께 모든 영역에서 일반적인 SOI n-MOSFET보다 $1.5\~1.7$배가 높음이 관찰 되었다. 이러한 경향은 실험 결과와 상당히 일치한다. 특히 strained Si의 두께가 10 nm 이하일 때 Si 채널 두께가 6 nm 보다 작은 SGOI n-MOSFET에서의 phonon-limited 전자 이동도는 일반 SOI n-MOSFET과 크게 달랐다. 우리는 이러한 차이가 전자들이 suained SGOI n-MOSFET의 반전층에서 SiGe층으로 터널링 했기 때문이고, 반면에 일반 SOI n-MOSFET에서는 캐리어 confinement 현상이 발생했기 때문인 것으로 해석하였다. 또한 우리는 10 nm와 3 nm 사이의 Si 두께에서는 SGOI n-MOSFET의 phonon-limited 전자 이동도가 inter-valley phonon 산란율에 영향을 받는 다는 것을 확인하였으며, 이러한 결과는 더욱 높은 드레인 전류를 얻기 위해서 15 nm 미만의 채널길이를 가진 완전공핍 C-MOSFET는 stained Si SGOI 구조로 제작하여야 함을 확인 했다 To make high-performance, low-power transistors beyond the technology node of 60 nm complementary metal-oxide-semiconductor field-effect transistors(C-MOSFETs) possible, the effect of electron mobility of the thickness of strained Si grown on a relaxed SiGe/SiO2/Si was investigated from the viewpoint of mobility enhancement via two approaches. First the parameters for the inter-valley phonon scattering model were optimized. Second, theoretical calculation of the electronic states of the two-fold and four-fold valleys in the strained Si inversion layer were performed, including such characteristics as the energy band diagrams, electron populations, electron concentrations, phonon scattering rate, and phonon-limited electron mobility. The electron mobility in an silicon germanium on insulator(SGOI) n-MOSFET was observed to be about 1.5 to 1.7 times higher than that of a conventional silicon on insulator(SOI) n-MOSFET over the whole range of Si thickness in the SOI structure. This trend was good consistent with our experimental results. In Particular, it was observed that when the strained Si thickness was decreased below 10 nm, the phonon-limited electron mobility in an SGOI n-MOSFT with a Si channel thickness of less than 6 nm differed significantly from that of the conventional SOI n-MOSFET. It can be attributed this difference that some electrons in the strained SGOI n-MOSFET inversion layer tunnelled into the SiGe layer, whereas carrier confinement occurred in the conventional SOI n-MOSFET. In addition, we confirmed that in the Si thickness range of from 10 nm to 3 nm the Phonon-limited electron mobility in an SGOI n-MOSFET was governed by the inter-valley Phonon scattering rate. This result indicates that a fully depleted C-MOSFET with a channel length of less than 15 m should be fabricated on an strained Si SGOI structure in order to obtain a higher drain current.
Bonded SOI wafer의 top Si과 buried oxide layer의 결함에 대한 연구
김석구,백운규,박재근,Kim Suk-Goo,Paik Un-gyu,Park Jea-Gun 한국재료학회 2004 한국재료학회지 Vol.14 No.6
Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).
정착시간과 레귤레이션 특성을 개선한 LDO(Low Dropout Regulator)의 설계
박경수(Kyung-Soo Park),박재근(Jea-Gun Park) 대한전기학회 2011 전기학회논문지 P Vol.60 No.3
A conventional LDO(Low Dropout Regulator) uses one OPAMP and one signal path. This means that OPAMP’s DC Gain and Bandwidth can’t optimize simultaneously within usable power. This also appears that regulation property and settling time of LDO can’t improve at the same time. Based on this idea, a proposed LDO uses two OPAMP and has two signal path. To improve regulation property, OPAMP where is used in the path which qualities DC gain on a large scale, bandwidth designed narrowly. To improve settling time, OPAMP where is used in the path which qualities DC gain small, bandwidth designed widely. A designed LDO used 0.5um 1P2M process and provided 200mA of output current. A line regulation and load regulation is 12.6㎷/V, 0.25㎷/㎃, respectively. And measured settling time is 1.5us in 5V supply voltage.
Cu-CMP에서 Alanine이 Cu와 TaN의 선택비에 미치는 영향
박진형,김민석,백운규,박재근,Park Jin-Hyung,Kim Min-Seok,Paik Ungyu,Park Jea-Gun 한국재료학회 2005 한국재료학회지 Vol.15 No.6
Chemical mechanical polishing (CMP) is an essential process in the production of integrated circuits containing copper interconnects. The effect of alanine in reactive slurries representative of those that might be used in copper CMP was studied with the aim of improving selectivity between copper(Cu) film and tantalum-nitride(TaN) film. We investigated the pH effect of nano-colloidal silica slurry containing alanine through the chemical mechanical polishing test for the 8(inch) blanket wafers as deposited Cu and TaN film, respectively. The copper and tantalum-nitride removal rate decreased with the increase of pH and reaches the neutral at pH 7, then, with the further increase of pH to alkaline, the removal rate rise to increase soddenly. It was found that alkaline slurry has a higher removal rate than acidic and neutral slurries for copper film, but the removal rate of tantalum-nitride does not change much. These tests indicated that alanine may improve the CMP process by controlling the selectivity between Cu and TaN film.
이중 음극층을 이용한 고휘도 전면발광(Top emission) 유기EL소자의 특성평가
강윤호,이수환,신동원,김성준,김달호,이곤섭,박재근,Kang, Yoon-Ho,Lee, Su-Hwan,Shin, Dong-Won,Kim, Sung-Jun,Kim, Dal-Ho,Lee, Gon-Sub,Park, Jea-Gun 한국반도체디스플레이기술학회 2006 반도체디스플레이기술학회지 Vol.5 No.3
Recently, Top emission organic light-emitting diode (TEOLED) has been attracted by their potential application for the development of flat panel display (FPD). We have fabricated the high luminance top emission organic-emitting diode (TEOLED) using dual cathode layer and three top emitting structure. These devices were characterized by electroluminescence (EL) and current density-voltage (J-V) measurements. After compared it with Au anode structure, luminance of the device using dual anode was better than using without Al device. Consequently, Al layers are very good candidates for a promising electron-injecting buffer layer for top emission light-emitting diode (TEOLED).
Al:Au 음극층을 이용한 양면발광(dual emission) 유기 EL 소자의 Al 두께별 특성 평가
이수환,김달호,양희두,김지헌,이곤섭,박재근,Lee, Su-Hwan,Kim, Dal-Ho,Yang, Hee-Doo,Kim, Ji-Heon,Lee, Gon-Sub,Park, Jea-Gun 한국반도체디스플레이기술학회 2008 반도체디스플레이기술학회지 Vol.7 No.1
The Al:Au double-layer metal electrode for use in transparent, dual emission of organic light-emitting diode (OLED) was fabricated. The electrode of Al:Au metals with various thicknesses was deposited by the vacuum thermal evaporation technique. For Al thickness of 1 nm, a bottom luminance of $4880\;cd/m^2$ was observed at 8 V. Otherwise, top luminance of $2020\;cd/m^2$ were observed at 8 V. In addition, the threshold voltages of the electrodes were 2.2 V. It was forward that the inserting 1 nm Al between LiF and Au enhanced electron injection with tunneling effect.
와이어 소잉 데미지 층이 단결정 실리콘 태양전지 셀 특성에 미치는 영향
김일환(Il-Hwan Kim ),박준성(Jun-Seong Park),박재근(Jea-Gun Park) 한국태양광발전학회 2018 Current Photovoltaic Research Vol.6 No.1
The dependency of the electrical characteristics of silicon solar-cells on the depth of damaged layer induced by wire-sawing process was investigated. To compare cell efficiency with residual sawing damage, silicon solar-cells were fabricated by using as-sawn wafers having different depth of saw damage without any damaged etching process. The damaged layer induced by wire-sawing process in silicon bulk intensely influenced the value of fill factor on solar cells, degrading fill factor to 57.20%. In addition, the photovoltaic characteristics of solar cells applying texturing process shows that although the initial depth of saw-damage induced by wire-sawing process was different, the value of short-circuit current, fill-factor, and power-conversion-efficiency have an almost same, showing ~17.4% of cell efficiency. It indicated that the degradation of solar-cell efficiency induced by wire-sawing process could be prevented by eliminating all damaged layer through sufficient pyramid-surface texturing process.
중금속 오염이 n형 실리콘 태양전지의 전기적 특성에 미치는 영향에 대한 연구
김일환(Il-Hwan Kim),박준성(Jun-Seong Park),박재근(Jea-Gun Park) 한국태양광발전학회 2018 Current Photovoltaic Research Vol.6 No.1
The dependency of the photovoltaic performance of p-/n-type silicon solar-cells on the metallic contaminant type (Fe, Cu, and Ni) and concentration was investigated. The minority-carrier recombination lifetime was degraded with increasing metallic contaminant concentration, however, the degradation sensitivity of recombination lifetime was lower at n-type than p-type silicon wafer, which means n-type silicon wafer have an immunity to the effect of metallic contamination. This is because heavy metal ions with positive charge have a much larger capture cross section of electron than hole, so that reaction with electrons occurs much more easily. The power conversion efficiency of n-type solar-cells was degraded by 9.73% when metallic impurities were introduced in the silicon bulk, which is lower degradation compared to p-type solar-cells (15.61% of efficiency degradation). Therefore, n-type silicon solar-cells have a potential to achieve high efficiency of the solar-cell in the future with a merit of immunity against metal contamination.