Determination of the Distribution and Morphology of Silicon Islandsin the Buried Oxide Layer of SOI Wafers by Using a Focused Ion Beamand Transmission Electron Microscope

심태헌,KIM Shin-Deuk,KIM Suk-Goo,박재근 한국물리학회 2004 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.45 No.1

Comparison of phonon-limited electron mobility in strained Si grown on silicon on insulator (sSOI) and SiGe on insulator (SGOI)

심태헌,박재근 한양대학교 세라믹연구소 2005 Journal of Ceramic Processing Research Vol.6 No.4

Through theoretical calculation, the phonon-limited electron mobility in fully depleted strained Si n-channel MOSFETs fabricated on silicon on insulator (i.e., sSOI) and SiGe on insulator (SGOI) was compared between the two structures as a function of Si thickness. In the Si thickness range from 10 nm down to 3 nm, the phonon-limited electron mobility in the sSOI n-MOSFET was about 1.5 times higher than that of a conventional SOI n-MOSFET. In particular, it was found that the electron mobility in the sSOI n-MOSFET was about 3% lower than that in the SGOI n-MOSFET. This difference can be attributed to two physical phenomena: first, that the sSOI n-MOSFET has higher inter-valley scattering rates than does the SGOI n-MOSFET, because of its greater carrier confinements: and second, that some electrons in the inversion layer of the SGOI n-MOSFET tunnel into the SiGe layer. These theoretical results are strongly consistent with previous experimental results.

Strained SGOI n-MOSFET에서의 phonon-limited전자이동도의 Si두께 의존성

심태헌,박재근,Shim Tae-Hun,Park Jea-Gun 대한전자공학회 2005 電子工學會論文誌-SD (Semiconductor and devices) Vol.42 No.9

60 nm C-MOSFET 기술 분기점 이상의 고성능, 저전력 트랜지스터를 구현 시키기 위해 SiGe/SiO2/Si위에 성장된 strained Si의 두께가 전자 이동도에 미치는 영향을 두 가지 관점에서 조사 연구하였다. 첫째, inter-valley phonon 산란 모델의 매개변수들을 최적화하였고 둘째, strained Si 반전층의 2-fold와 4-fold의 전자상태, 에너지 밴드 다이어그램, 전자 점유도, 전자농도, phonon 산란율과 phonon-limited 전자이동도를 이론적으로 계산하였다. SGOI n-MOSFET의 전자이동도는 고찰된 SOI 구조의 Si 두께 모든 영역에서 일반적인 SOI n-MOSFET보다 $1.5\~1.7$배가 높음이 관찰 되었다. 이러한 경향은 실험 결과와 상당히 일치한다. 특히 strained Si의 두께가 10 nm 이하일 때 Si 채널 두께가 6 nm 보다 작은 SGOI n-MOSFET에서의 phonon-limited 전자 이동도는 일반 SOI n-MOSFET과 크게 달랐다. 우리는 이러한 차이가 전자들이 suained SGOI n-MOSFET의 반전층에서 SiGe층으로 터널링 했기 때문이고, 반면에 일반 SOI n-MOSFET에서는 캐리어 confinement 현상이 발생했기 때문인 것으로 해석하였다. 또한 우리는 10 nm와 3 nm 사이의 Si 두께에서는 SGOI n-MOSFET의 phonon-limited 전자 이동도가 inter-valley phonon 산란율에 영향을 받는 다는 것을 확인하였으며, 이러한 결과는 더욱 높은 드레인 전류를 얻기 위해서 15 nm 미만의 채널길이를 가진 완전공핍 C-MOSFET는 stained Si SGOI 구조로 제작하여야 함을 확인 했다 To make high-performance, low-power transistors beyond the technology node of 60 nm complementary metal-oxide-semiconductor field-effect transistors(C-MOSFETs) possible, the effect of electron mobility of the thickness of strained Si grown on a relaxed SiGe/SiO2/Si was investigated from the viewpoint of mobility enhancement via two approaches. First the parameters for the inter-valley phonon scattering model were optimized. Second, theoretical calculation of the electronic states of the two-fold and four-fold valleys in the strained Si inversion layer were performed, including such characteristics as the energy band diagrams, electron populations, electron concentrations, phonon scattering rate, and phonon-limited electron mobility. The electron mobility in an silicon germanium on insulator(SGOI) n-MOSFET was observed to be about 1.5 to 1.7 times higher than that of a conventional silicon on insulator(SOI) n-MOSFET over the whole range of Si thickness in the SOI structure. This trend was good consistent with our experimental results. In Particular, it was observed that when the strained Si thickness was decreased below 10 nm, the phonon-limited electron mobility in an SGOI n-MOSFT with a Si channel thickness of less than 6 nm differed significantly from that of the conventional SOI n-MOSFET. It can be attributed this difference that some electrons in the strained SGOI n-MOSFET inversion layer tunnelled into the SiGe layer, whereas carrier confinement occurred in the conventional SOI n-MOSFET. In addition, we confirmed that in the Si thickness range of from 10 nm to 3 nm the Phonon-limited electron mobility in an SGOI n-MOSFET was governed by the inter-valley Phonon scattering rate. This result indicates that a fully depleted C-MOSFET with a channel length of less than 15 m should be fabricated on an strained Si SGOI structure in order to obtain a higher drain current.

Characterization of nano-scale strained silicon-on-insulator substrates by multi-wavelength high resolution micro-raman and optical reflectance

심태헌,이두영,김태현,박재근 한양대학교 세라믹연구소 2014 Journal of Ceramic Processing Research Vol.15 No.1

Strained silicon-on-insulator (sSOI) substrates were characterized using multi-wavelength, high resolution, polychromatorbased micro Raman spectroscopy and normal incidence optical reflectance spectra measurement. Significant Raman shifts towards the lower wavenumber side, corresponding to tensile stress, and broadening of the Raman peak in sSOI thin films were observed. The stress and crystallinity of sSOI were characterized from the shift and full-width-at-half-maximum data. The thickness of strained Si and buried oxide film of sSOI was estimated from the optical reflectance. Multi-wavelength Raman and optical reflectance measurement, when used together provide a useful and practical non-destructive stress, and structural characterization technique for nano-scale sSOI.

Strained Si/Relaxed SiGe/SiO2/Si 구조 FD n-MOSFET의 전자이동에 Ge mole fraction과 strained Si 층 두께가 미치는 영향

백승혁,심태헌,문준석,차원준,박재근 대한전자공학회 2004 電子工學會論文誌-SD (Semiconductor and devices) Vol.41 No.10

SOI 구조에서 형성된 MOS 트랜지스터의 장점과 strained Si에서 전자의 이동도가 향상되는 효과를 동시에 고려하기 위해 buried oxide(BOX)층과 Top Si층 사이에 Ge을 삽입하여 strained Si/relaxed SiGe/SiO₂Si 구조를 형성하고 strained Si fully depletion(FD) n-MOSFET를 제작하였다. 상부 strained Si층과 하부 SiGe층의 두께의 합을 12.8nm로 고정하고 상부 strained Si 층의 두께에 변화를 주어 두께의 변화가 electron mobility에 미치는 영향을 분석하였다. Strained Si/relaxed SiGe/SiO2/Si (strained Si/SGOI) 구조위의 FD n-MOSFET의 전자 이동도는 Si/SiO₂/Si (SOI) 구조위의 FD n-MOSFET 에 비해 30-80% 항상되었다. 상부 strained Si 층과 하부 SiGe 층의 두께의 합을 12.8nm 로 고정한 shrined Si/SGOI 구조 FD n-MOSFET에서 상부층 strained Si층의 두께가 감소하면 하부층 SiGe 층 두께 증가로 인한 Ge mole fraction이 증가함에 의해 inter-valley scattering 이 감소함에도 불구하고 n-channel 층의 전자이동도가 감소하였다. 이는 strained Si층의 두께가 감소할수록 2-fold valley에 있는 전자가 n-channel 층에 더욱더 confinement 되어 intra-valley phonon scattering 이 증가하여 전자 이동도가 감소함이 이론적으로 확인되었다. In order to enhance the electron mobility in SOI n-MOSFET, we fabricated fully depletion(FD) n-MOSFET on the strained Si/relaxed SiGa/SiO$_2$/Si structure(strained Si/SGOI) formed by inserting SiGe layer between a buried oxide(BOX) layer and a top silicon layer. The summated thickness of the strained Si and relaxed SiGe was fixed by 12.8 nm and then the dependency of electron mobility on strained Si thickness was investigated. The electron mobility in the FD n-MOSFET fabricated on the strained Si/SGOI enhanced about 30-80% compared to the FD n-MOSFET fabricated on conventional SOI. However, the electron mobility decreased with the strained Si thickness although the inter-valley phonon scattering was reduced via the enhancement of the Ge mole fraction. This result is attributed to the increment of intra-valley phonon scattering in the n-channel 2-fold valley via the further electron confinement as the strained Si thickness was reduced.

Effect of nano-scale strained Si layer grown on SiGe-on-insulator structure on MOSFET drain current improvement

이곤섭,심태헌,박재근 한양대학교 세라믹연구소 2004 Journal of Ceramic Processing Research Vol.5 No.3

Utilizing low-temperature epitaxial technology, we have developed a novel MOSFET structure consisting of a nano- scale (< 15nm) strained Silicon (Si) layer grown on a nano-scale SiGe-on-insulator (SiGe-OI) structure. By fabricating n- MOSFETs based on this strained Si/SiGe/SiO2/Si structure, we experimentally studied two effects on the electron mobility in the inversion layer,as compared to MOSFETs based on the conventional silicon on insulator (SOI) structure: the effect of the Ge mole fractionin the SiGe layer, and the effect of the strained Si layer thickness. We observed that the current transport in the strained Silayer was enhanced by a factor of about 1.6 as compared to the unstrained Si in the conventional case. In addition, we foundthat in the case of a strained Si layer with a thickness of less than 15 nm, as the its thickness was reduced, the electron mobilityin the inversion layer decreased.

Effect of Interface Thickness on Power Conversion Efficiency of Polymer Photovoltaic Cells

이수환,김지헌,심태헌,박재근 대한금속·재료학회 2009 ELECTRONIC MATERIALS LETTERS Vol.5 No.1

We investigated the effect of the thicknesses of the interface layers (here, PEDOT:PSS and LiF) of polymer photovoltaic cells because variations in thickness strongly affect the power conversion efficiency (PCE). It was observed that the PCE rapidly increased with a PEDOT:PSS thickness of up to ~2,000 rpm and rapidly decreased when the PEDOT:PSS was thicker than ~2,000 rpm. A PCE of 6.648% was obtained at a specific PEDOT:PSS layer thickness of ~2,000 rpm, about 41.5% (from 4.698 to 6.648%) higher than the PCE with no PEDOT:PSS layer. In addition, the PCE slightly increased with an LiF layer thickness of up to ~0.5 nm and rapidly decreased when the LiF layer was thicker than ~0.5 nm. The maximum PCE was obtained at the LiF layer thickness of ~0.5 nm. In particular, the maximum values of PCE, Jsc, Voc, and FF were obtained at 6.827%, 15.74 mA/cm2, 0.665 V, and 0.652, respectively. The PCE increased 209.2% (from 2.028 to 6.827%), compared to the LiF layer thickness of ~5 nm.

Post-RTA Effect on the Electrical Characteristics ofNano-Scale Strained Si Grown on SiGe-on-Insulator n-MOSFET

김성재,박재근,정명호,심태헌,조원주 한국물리학회 2007 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.50 No.2

The effect of the surface roughness of strained Si grown on relaxed SiGe-on-insulator on the electrical characteristics of n-MOSFETs was investigated. The surface roughness-induced degradations of the driving current and leakage current were minimized by applying, after conventional rapid thermal annealing (RTA), an additional furnace annealing consisting of 30 min in a N$_2$ ambient at 500 $^\circ$C. The improvements resulted from the post-RTA process decreasing the charge density of the interface state.

Electrical behavior of ultra-thin body silicon-on-insulator n-MOSFETs at a high operating temperature

Seong-Je Kim,심태헌,박재근 한양대학교 세라믹연구소 2009 Journal of Ceramic Processing Research Vol.10 No.4

Recessed ultra-thin body (UTB) silicon-on-insulator (SOI) n-meta-oxide-semiconductor field-effect transistors (MOSFETs) with a top silicon thickness of less than 10 nm were successfully fabricated. We investigated the dependence of their electrical characteristics, such as subthreshold conduction and effective mobility, on the operating temperature the different channel thicknesses of less than 10 nm. In the case of a 4.5-nm-channel UTB SOI n-MOSFET, it was observed that as the temperature rises, the subthreshold conduction characteristic became sensitive to temperature, while the leakage current was insensitive to temperature. In addition, the effective mobility of a 4.5-nm-thick UTB SOI n-MOSFET decreased because the carrier transport was suppressed by scatterings both from surface and interface roughness scatterings. In particular, we confirmed that mobility differences at the effective fields of 0.1 and 0.3MV/cm decrease with a rise in temperature resulting from the mobility being dominated by phonon scattering rather than scatterings from surface roughness.

Hole Mobility Enhancement in Strained SiGe Grown on Silicon-on-Insulator p-MOSFETs

Seong-Je Kim,백지영,심태헌,이훈주,박재근,김관수,조원주 한국물리학회 2008 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.53 No.4

The hole mobility of p-metal-oxide-semiconductor field-effect transistors (MOSFETs) with a compressively-strained SiGe channel grown on a silicon-on-insulator (SOI) structure was investigated. In particular, the dependence of the mobility behavior on the effective field (Eeff ) was investigated by varying the Ge concentration in the SiGe layer. We observed that the mobility enhancement factor increased with both the Ge concentration and the Eeff . In addition, we confirmed that the hole mobility enhancement factor caused by the compressively-strained SiGe channel grown on a SOI structure persisted in the higher Eeff range and that it was higher than that of the silicon channel structure. This was due to the fact that the strain and the confinement effects both work to maintain a constant energetic splitting between the heavy hole and the light hole bands.