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고재문,서준용 울산대학교 1997 공학연구논문집 Vol.28 No.1
본 논문에서는 개체지향 프로그래밍 개념을 이용하여 네트워크 모형의 전산 구현 통합패키지를 개발하였다. 네트워크 모형을 표현하기 위하여 내부적으로 단일 연결리스트를 채택하였다. 풀-다운 메뉴 방식을 이용하여 파일, 자료 입출력, 그리기, 문제선택 메뉴를 구성하였다. 자료입력의 경우 마우스를 이용한 입력, 고밀도 네트워크에 대한 파일 입력, 저밀도 네트워크에 대한 파일 입력의 3가지 방식을 제시하였다. 현실감을 높이기 위해 모형을 그래픽으로 나타낼 수 있도록 하였다. 또한 사용자가 자신의 환경에 따라 선택이 가능하도록 고밀도 및 저밀도 자료형식으로 저장이 가능하도록 하였다. 응용 예를 위하여 최단경로나무문제, 최소걸침나무문제, 최대흐름문제의 해법을 첨가하였으며, 사용자는 자신의 문제에 대한 해법을 서브루틴으로 추가할 수 있도록 하였다. 개체지향개념을 이용하였기 때문에 네트워크 모형을 쉽게 확장할 수 있으며 프로그램을 재사용할 수도 있다. 따라서 사용자는 네트워크 모형을 전산구현하는데 드는 노력을 대폭 경감시킬 수 있다. An integrated computer-package for the network model is developed, where the network model is implemented using object-oriented programming. Node object, arc object and network object are defined a user-defined objects. Singly linked list is adopted as the internal data structure for network representation. All works are designed to be implemented through the pull-down menu. The main menu consists of FILE, INPUT TYPE, DRAWING, and PROBLEM SELECTION. Three methods are suggested for data input: mouse input, file input for dense-type data, and file input for sparse-type data. The model can be displayed graphically for the sense of reality. It can be stored in both dense-type and sparse-type data format, which enables the user to fit the model to his/her environment. Shortest path tree problem, minimum spanning tree problem, and maximal flow problem are applied for illustrations. Since the network model is realized using the object-oriented concept, the user can apply any problem with its own subroutine. The object-oriented programming gives the benefit of modifying or expanding the model easily and reusing the program. As a result, the user can dramatically save time and efforts for implementing the network model.
A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO
Seo, Jin-Cheol,Moon, Yong-Hwan,Seo, Joon-Hyup,Jang, Jae-Young,An, Taek-Joon,Kang, Jin-Ku The Institute of Electronics and Information Engin 2013 Journal of semiconductor technology and science Vol.13 No.3
In this paper, a clock and data recovery (CDR) circuit that supports triple data rates of 1.62, 2.7, and 5.4 Gbps for DisplayPort 1.2 standard is described. The proposed CDR circuit covers three different operating frequencies with a single VCO switching the operating frequency by the 3-bit digital code. The prototype chip has been designed and verified using a 65 nm CMOS technology. The recovered-clock jitter with the data rates of 1.62/2.7/5.4 Gbps at $2^{31}$-1 PRBS is measured to 7/5.6/4.7 $ps_{rms}$, respectively, while consuming 11 mW from a 1.2 V supply.
Moon, Joon Ho,Kim, Ji Ho,Im, Hyung-Jun,Lee, Dong Soo,Park, Eun Jung,Song, Kilyoung,Oh, Hyun Ju,Hyun, Su Bin,Kang, Sang Chul,Kim, Hyunil,Moon, Hyo Eun,Park, Hyung Woo,Lee, Hong Jae,Kim, Eun Ji,Kim, Seo The Korean Society for Brain and Neural Science 2014 Experimental Neurobiology Vol.23 No.3
<P>Destruction of dopaminergic neurons in the substantia nigra pars compacta (SNpc) is a common pathophysiology of Parkinson's disease (PD). Characteristics of PD patients include bradykinesia, muscle rigidity, tremor at rest and disturbances in balance. For about four decades, PD animal models have been produced by toxin-induced or gene-modified techniques. However, in mice, none of the gene-modified models showed all 4 major criteria of PD. Moreover, distinguishing between PD model pigs and normal pigs has not been well established. Therefore, we planned to produce a pig model for PD by chronic subcutaneous administration of 1-methyl-4-phenyl-1,2,3,6-tetrahydropyridine (MPTP), neurotoxin. Changes in behavioral patterns of pigs were thoroughly evaluated and a new motor scoring system was established for this porcine model that was based on the Unified Parkinson's Disease Rating Scale (UPDRS) in human PD patients. In summary, this motor scoring system could be helpful to analyze the porcine PD model and to confirm the pathology prior to further examinations, such as positron emission tomography-computed tomography (PET-CT), which is expensive, and invasive immunohistochemistry (IHC) of the brain.</P>
방송콘텐츠의 서비스속성이 해외 한국어방송사에 대한 만족도에 미치는 영향
문준서(Joon-Seo Moon),박기성(Ki-Sung Park),송종현(Chong-Hyun Song) 한국콘텐츠학회 2011 한국콘텐츠학회논문지 Vol.11 No.10
본 연구는 최근 침체위기를 맞고 있는 해외 한국어방송사들의 방송서비스 개선방안을 모색하기 위해 해외 교민들을 대상으로 방송콘텐츠 서비스의 주요 속성이 방송을 송출하는 해외 한국어방송사의 만족도에 영향을 미치는 과정을 탐색적으로 분석하였다. 본 연구에서는 해외 한국어방송사가 주로 제공하는 서비스를 방송콘텐츠의 완성도, 방송콘텐츠 제공의 효율성, 방송콘텐츠의 공익성이라는 세 가지의 틀로 구분하였고, 이러한 세가지 속성이 방송사에 대한 만족도에 영향을 주는 주요 요인으로 설정하였다. 또한 방송사의 내적요인과 외적요인이 방송사의 만족도에 직접적으로 영향을 주는 요인으로 설정하였다. 이러한 연구모형을 시청률이 낮은 집단과 높은 집단을 나누어 비교분석함으로써 해외한국어방송사에 대한 만족도 촉진을 향상시키기 위한 현실적인 대안을 제시하였다. The purpose of this research is to seek for improvements in the services provided by the Korean broadcasting services overseas that face stagnation in the industry. Therefore, the research bases its observation on analyzation of the influences the principal attributes of the broadcasting service contents has on the satisfaction of the overseas Korean viewers. This research classifies broadcasting services into three categories; degree of completion, effectiveness, and public interest. It further established such elements and the internal and external cognitive factors of broadcasting company as factors of direct influence on the level of satisfaction. This study suggests practical alternatives as solution through comparative analysis between the group with low viewer rating and the group with high viewer rating in accordance to the above mentioned research framework.
A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO
Jin-Cheol Seo,Yong-Hwan Moon,Joon-Hyup Seo,Jae-Young Jang,Taek-Joon An,Jin-Ku Kang 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.3
In this paper, a clock and data recovery (CDR) circuit that supports triple data rates of 1.62, 2.7, and 5.4 Gbps for DisplayPort 1.2 standard is described. The proposed CDR circuit covers three different operating frequencies with a single VCO switching the operating frequency by the 3-bit digital code. The prototype chip has been designed and verified using a 65 nm CMOS technology. The recovered-clock jitter with the data rates of 1.62/2.7/5.4 Gbps at 2<SUP>31</SUP>-1 PRBS is measured to 7/5.6/4.7 psrms, respectively, while consuming 11 ㎽ from a 1.2 V supply.