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이상 패턴 분석을 통한 정책의 적합성 분석 연구 : S 시의 아동 급식 전자 카드 사례를 중심으로
전종식,권오병 한국IT서비스학회 2018 한국IT서비스학회지 Vol.17 No.1
E-Card Service for Child Nutrition Program is one of the main public policy services nowadays. In case of inconvenience during the use of the e-cards, it is recommended to cooperate with related organizations in order to promptly handle and provide guidance, and thoroughly manage child feeding service such as hygiene, nutrition and kindness etc. To do so, it is very important to provide food service that meets local actual conditions and children's needs in a cost effective manner for the underage who are worried about the poorly-fed by understanding the pattern of child feeding e-card service. Hence. this paper aims to investigate how child feeding e-card service efficiently provides meals according to the local situation and children's needs through big data analysis and to propose a method of identifying welfare conditions according to the purpose of service with actual application examples. The results suggest that, first of all, this study is able to judge appropriateness of public institution’s policy in a timely and repetitive manner through non-standard data analysis such as Naver News and transaction data. Secondly, this paper proposes a multi-layered analysis framework, which performs online open data analysis to detect policy issues, visualizes retrieval and preprocessing of real data, and performs abnormal pattern recognition. These will be worthy of reference to other similar projects.
전종식,조양기,김희석 청주대학교 산업과학연구소 2000 産業科學硏究 Vol.17 No.2
Recently, Field Programmable Gate Array(FPGAs) and Complex Programmable Logic Device(CPLDs) make a role of rapid prototyping. Therefore many studies for techonolgy mapping algorithm of FPGAs are performed. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table(LUT)-based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams(BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks(CLBs) in FPGAs. The experimental results on a set of benchmarks show that our algorithm can produce much better results than the similar works of the previous approaches.
전종식,김재진,김희석 청주대학교 산업과학연구소 1999 産業科學硏究 Vol.17 No.1
In this paper, We propose a high level synthesis method targeting low power consumption for data dominated CMOS circuits. The high level synthesis is divided into three basic tasks: scheculing, resource and register allocation. For lower power scheduling, we increase the possibility of reusing an input operand of functional units. For a scheduled data flow graph a compatibility graph for register and resource allocation is formed, and then a special weighted network is then constructed from the compatibility graph and the minimum cost flow algorithm is performed on the network th obtain the minimum power consumption data path assignment. The formulated problem is then solved optimally in polynomial time. This method reduces the switching activity. Experimental results show 14.6% power reduction in benchmark circuits.