CMOS의 설계 파라미터 및 Cascode단의 변화에 따른 Time-Domain Temperature Sensor 특성에 관한 연구

우솔아,김진세,금종민,경신수,성만영 한국과학기술원 반도체설계교육센터 2015 IDEC Journal of Integrated Circuits and Systems Vol.1 No.1

This paper presents low power and high speed on-chip temperature sensor only using two ring-oscillators which have different CMOS delay characteristics, counters and Time-to-Digital Converters (TDC) to maintain the performance benefit of CMOS digital circuit. This novel temperature sensor does not require any bias circuits or reference external clocks. The novel temperature sensor measures the delay variations between the temperature-dependent signal generator and the temperature-independent signal generator according to temperature. The generating two signals is sensed by TDC. But, temperature sensor of TDC cells, which was used to measure the delay time of two CMOS delay characteristics and convert to digital outputs, occupies large chip area. To overcome this problem, we designed an advanced temperature sensor using Coarse-Fine TDC. Also, it has a higher resolution than existing temperature sensor. After checking the performance of the temperature sensor using a HSPICE simulation, the chip was manufactured using the Dongbu 0.11μm CMOS process and verified. 본 논문에서는 서로 다른 CMOS Delay 특성을 갖는 2개의 링 오실레이터와 카운터, Time-to-Digital Converter(TDC)를 이용한 Digital On-Chip 온도 감지 센서를 설계하였다. 본 논문에서 제안한 온도 감지 센서는 신호 발생 단과 신호 출력 단으로 구성된다. 신호 발생 단은 CMOS로 구성된 링 오실레이터와 카운터로 구성되어 있고, CMOS의 Cascode단을 쌓음으로써 온도에 대한 민감도를 제어할 수 있다. 따라서 온도에 민감한 링 오실레이터와 온도에 민감하지 않은 링 오실레이터를 설계하고, 카운터를 이용하여 두 신호의 펄스 너비를 증폭시켰다. 신호 발생 단에서 발생된 신호는 신호 출력 단으로 인가된다. 신호 출력 단은 TDC로 구성하여 온도 변화를 디지털 코드로 감지할 수 있다. 온도 감지 센서는 -20∼120℃를 감지할 수 있도록 설계하였다. 또한 제안한 온도 감지 센서에서는 Chip 면적을 최소화하기 위해 Coarse TDC와 Fine TDC를 이용하여 설계하였다. 이를 통해 고 분해능을 갖는 온도 감지 센서를 설계하였고, HSPICE simulation을 통해 온도 감지 센서의 성능을 검증하였다. Chip은 동부 0.11um CMOS 공정으로 제작하여 측정하였다.

Counter-Based Frequency Discriminator for Fine Dust Sensor

박선의,박한기,김주엽,방주은,신유환,최재혁 한국과학기술원 반도체설계교육센터 2023 IDEC Journal of Integrated Circuits and Systems Vol.9 No.2

This work presents a counter-based frequency discriminator for a fine dust sensor. Detecting the frequency variations of MEMS resonator according to the fine dust concentration, the proposed frequency discriminator provides digital codes which represents the frequency variations. Since the proposed frequency discriminator is based on the CMOS process, it achieved extremely small area and low power of 0.3 mW, which facilitates the integration into portable devices. The proposed counter-based frequency discriminator covers the input frequency range of 1.6 to 2.4 GHz with a resolution of 50 kHz. Since it has a flexible divider, its resolution and detection speed can be flexibly changed.

Analysis of the TEG Maximum Power Point Tracking Operation with Continuously Scalable-Conversion-Ratio SC Converter

김현진,김철우 한국과학기술원 반도체설계교육센터 2023 IDEC Journal of Integrated Circuits and Systems Vol.9 No.2

This paper analyzes the output power of the thermoelectric generator (TEG) and continuously scalable-conversion-ratio SC converter for achieving low-power maximum power point tracking (MPPT) with switched-capacitor (SC) converter. In state-of-the-art SC energy harvesting interfaces, they transfer harvested power inefficiently due to fixed conversion ratios. Therefore, the proposed MPPT method harvest power based on the conventional open circuit voltage method, without additional open circuit voltage sampling period. The proposed energy harvesting converter is designed in a 180 nm CMOS process and is measured to prove that the power can be transferred properly with the analyzed power conversion modes.

An Evaluation and Comparison of State-of-the-Art Flip-Flops for Low-Power Applications

강경훈,정완영 한국과학기술원 반도체설계교육센터 2023 IDEC Journal of Integrated Circuits and Systems Vol.9 No.2

Flip-Flop (FF) is the basic block of sequential digital circuits, which has a significant impact on the speed, power, and stability of digital systems. Reducing the power consumption of FFs is an attractive solution for attaining good energy efficiency of digital systems. However, the conventional TGFF (Transmission-gate flip-flop) consumes excessive dynamic power at clock inverters even though the data transition does not occur. To eliminate redundant clock transitions, some techniques are applied. This paper analyzes and compares recently published low-power FFs in 65 nm CMOS.

A 10 Gbps Optical Receiver Analog Front-End and MZM Driver in 65nm CMOS

에이큐,이상국 한국과학기술원 반도체설계교육센터 2023 IDEC Journal of Integrated Circuits and Systems Vol.9 No.2

This paper presents a 10 Gbps optical receiver analog front end and a Mach-Zehnder Modulator (MZM) driver in the 65nm technology. The receiver consists of a Shunt Feedback TIA and a Limiting Amplifier with active feedback for bandwidth enhancement. Offset cancellation is also implemented in the feedback path to minimize random and systematic offsets. The modulator driver adopts a dual-stacked buffer topology with dynamic biasing to generate a high voltage swing. The measured trans-impedance gain of the receiver analog front-end is 74.31 dBΩ with a bandwidth of 16.87 GHz. The DC power consumption is 153 mW (including output buffer) with a supply voltage of 1.8 V. The total chip area of the receiver analog front-end is 0.605 mm2. The modulator driver achieves a measured voltage swing of 2.02 Vpp @ 10 Gbps and a simulated average dynamic power of 230 mW @ 10 Gbps with supply voltages of 1.1 and 2.2 V. The total chip area of the modulator driver is 0.434 mm2.

Design of InP HBT 230-GHz Frequency Multiplier Chain with a Multiplication Factor of 18

민상기,금우용,손희강,유정환,김도윤,이재성 한국과학기술원 반도체설계교육센터 2023 IDEC Journal of Integrated Circuits and Systems Vol.9 No.2

A x18 frequency multiplier chain has been designed in this work based on a 250-nm InP HBT technology. Three frequency multipliers are cascaded to form the integrated frequency multiplier chain: a 38-GHz frequency tripler, a 115-GHz frequency tripler, and a 230-GHz frequency doubler. The performances of the circuits are characterized based on simulation and presented in this paper, which will be verified with measurement when chip fabrication is completed. The 38-GHz cascode frequency tripler shows a saturated output power of 2.6 dBm at 38.3 GHz, while the 115-GHz single-balanced differential tripler exhibits an output power of 2.3 dBm at 115 GHz. With the 230-GHz frequency doubler, saturated output power of 3.2 dBm was obtained. The fully integrated multiplier chain shows a saturation output power of -3.4 dBm at 230 GHz, with a peak conversion gain obtained as -2.9 dB at an input power of -1.0 dBm. The 3-dB bandwidth is 27 GHz, covering a frequency range of 223 - 250 GHz.

A 1.2V 30 MS/s SAR ADC with Foreground Capacitor Calibration

주현규,이세원,이민재 한국과학기술원 반도체설계교육센터 2019 IDEC Journal of Integrated Circuits and Systems Vol.5 No.2

– In this paper, a successive approximation register (SAR) ADC with foreground capacitor calibration is presented. In order to overcome the drawback of SAR architecture with low-power consumption, several techniques are adopted such as high-speed latch, three-stage comparator, reference-less architecture, custom metal-oxide-metal (MOM) capacitor, and foreground capacitor calibration. The design methodology and measurement procedure is presented in detail. The prototype ADC is fabricated in a 65 nm CMOS process, and it achieves signal-to-noise and distortion ratio (SNDR) over 60 dB at sampling frequency of 30 MS/s under 1.2 V supply voltage. The power consumption is 1.1 mW, and the chip area of the core ADC is 0.045 mm2.

캐패시터 에러가 보상된 13-b SAR ADC

박범진,하현수,심재윤 한국과학기술원 반도체설계교육센터 2016 IDEC Journal of Integrated Circuits and Systems Vol.2 No.1

본 논문에서는 극소전력 센서를 위한 13-b successive approximation register(SAR) 아날로그 디지털 변환기(ADC)에 대하여 다룬다. 디지털 아날로그 변환기의 두 개의 동일한 캐패시터 뱅크의 role-swapping을 통하여 캐패시터 에러를 보정할 수 있다. 제안된 ADC는 0.13um standard CMOS 공정으로 제작되었다. 0.5V의 공급 전압을 사용하였고, 변환 범위는 rail-to-rail, 40kS/s의 샘플링 레이트에서 1.47uW의 전력을 소모한다. Figure-of-Merit(FOM)은 17.9 fJ/conversion-step이며 ENOB는 11-b 이다. A 13-b successive approximation analog-to -digital converter (ADC) is presented for ultra -low-power sensor interface. Capacitor error compensation is achieved by swapping the roles of two identical capacitor banks in DAC. The ADC is implemented in a standard 0.13‑μm CMOS. With a single supply voltage of 0.5 V and a rail-to-rail conversion range, ADC dissipates 1.47 μW at a sampling rate of 40 kS/s. It shows an FoM of 17.9 fJ/conversion-step with ENOB of 11.0-b.

300-GHz Integrated Heterodyne Receiver Chain for Phased-Array with Wide IF Bandwidth

박건우,이승종,한인수,전상근 한국과학기술원 반도체설계교육센터 2021 IDEC Journal of Integrated Circuits and Systems Vol.7 No.4

This paper presents a fully integrated terahertz receiver chain for phased-array with a wide IF bandwidth designed using a 250-nm InP double heterojunction bipolar transistor (DHBT) technology. The phased-array receiver chain consists of a variable-gain low-noise amplifier (VG-LNA), phase shifter, down-conversion mixer, and injection locking local oscillator (ILO). Each circuit block is designed to be broadband to achieve a wide receiver chain bandwidth. The VG-LNA adopts cascaded amplifying stages with a current steering technique to control the gain. While the control voltage (Vcon) varies from 2 to 3.6 V, the gain varies from 15.6 to 0 dB at 300 GHz. The noise figure is no higher than 15 dB at all Vcon conditions. The phase shifter uses a current combining structure based on Gilbert cells. The peak conversion gain is -10 dB at 303 GHz and the 3 dB bandwidth is 52 GHz extending from 270 to 322 GHz. The LO employs an injection locking technique. The locking range is from 260 to 328 GHz (22.7%) when a 10-dBm signal is injected. The maximum output power is 0.5 dBm at 300 GHz. The Gilbert-cell-based down-conversion mixer shows a 72-GHz bandwidth extending from 252 GHz to 324 GHz. The proposed fully integrated phased-array receiver chain shows a wide bandwidth characteristic. When the control voltage is set to 2.0 V, the peak conversion gain is 12.3 dB and the 3-dB bandwidth reaches 45 GHz from 270 GHz to 315 GHz.

Continuous-time delta-sigma modulator using asynchronous SAR quantizer and digital ΔΣ Truncator

신종윤,박상규 한국과학기술원 반도체설계교육센터 2018 IDEC Journal of Integrated Circuits and Systems Vol.4 No.3

As the demand for IoT related devices has increased recently, the demand for voice sensors used in these devices is increasing. Low power is a key factor because these devices have to run on batteries for long periods of time. A delta-sigma modulator is best suited for analog-to-digital converters used in the voice signal band because resolution is more important than speed. This delta sigma modulator requires a high SQNR in order to obtain high resolution, indicating that a high bit number quantizer is required. However, a high bit number quantizer requires a large number of comparators and DACs, which increases power consumption and takes up a large area. In this paper, to achieve low noise and low power dissipation, 3rd order continuous time delta-sigma (DS) ADC with a 6-bit asynchronous successive approximation register (ASAR) quantizer and a digital delta-sigma truncator which reduce a number of DACs is presented. The designed ADC front-end has been implemented through a 180 nm CMOS process and achieved 86 dB SNR and 76 dB SNDR over a 20 kHz signal band. The total chip dissipates a power of 170μW from a 1.5 V supply.