CMOS의 설계 파라미터 및 Cascode단의 변화에 따른 Time-Domain Temperature Sensor 특성에 관한 연구

우솔아,김진세,금종민,경신수,성만영 한국과학기술원 반도체설계교육센터 2015 IDEC Journal of Integrated Circuits and Systems Vol.1 No.1

This paper presents low power and high speed on-chip temperature sensor only using two ring-oscillators which have different CMOS delay characteristics, counters and Time-to-Digital Converters (TDC) to maintain the performance benefit of CMOS digital circuit. This novel temperature sensor does not require any bias circuits or reference external clocks. The novel temperature sensor measures the delay variations between the temperature-dependent signal generator and the temperature-independent signal generator according to temperature. The generating two signals is sensed by TDC. But, temperature sensor of TDC cells, which was used to measure the delay time of two CMOS delay characteristics and convert to digital outputs, occupies large chip area. To overcome this problem, we designed an advanced temperature sensor using Coarse-Fine TDC. Also, it has a higher resolution than existing temperature sensor. After checking the performance of the temperature sensor using a HSPICE simulation, the chip was manufactured using the Dongbu 0.11μm CMOS process and verified. 본 논문에서는 서로 다른 CMOS Delay 특성을 갖는 2개의 링 오실레이터와 카운터, Time-to-Digital Converter(TDC)를 이용한 Digital On-Chip 온도 감지 센서를 설계하였다. 본 논문에서 제안한 온도 감지 센서는 신호 발생 단과 신호 출력 단으로 구성된다. 신호 발생 단은 CMOS로 구성된 링 오실레이터와 카운터로 구성되어 있고, CMOS의 Cascode단을 쌓음으로써 온도에 대한 민감도를 제어할 수 있다. 따라서 온도에 민감한 링 오실레이터와 온도에 민감하지 않은 링 오실레이터를 설계하고, 카운터를 이용하여 두 신호의 펄스 너비를 증폭시켰다. 신호 발생 단에서 발생된 신호는 신호 출력 단으로 인가된다. 신호 출력 단은 TDC로 구성하여 온도 변화를 디지털 코드로 감지할 수 있다. 온도 감지 센서는 -20∼120℃를 감지할 수 있도록 설계하였다. 또한 제안한 온도 감지 센서에서는 Chip 면적을 최소화하기 위해 Coarse TDC와 Fine TDC를 이용하여 설계하였다. 이를 통해 고 분해능을 갖는 온도 감지 센서를 설계하였고, HSPICE simulation을 통해 온도 감지 센서의 성능을 검증하였다. Chip은 동부 0.11um CMOS 공정으로 제작하여 측정하였다.

캐패시터 에러가 보상된 13-b SAR ADC

박범진,하현수,심재윤 한국과학기술원 반도체설계교육센터 2016 IDEC Journal of Integrated Circuits and Systems Vol.2 No.1

본 논문에서는 극소전력 센서를 위한 13-b successive approximation register(SAR) 아날로그 디지털 변환기(ADC)에 대하여 다룬다. 디지털 아날로그 변환기의 두 개의 동일한 캐패시터 뱅크의 role-swapping을 통하여 캐패시터 에러를 보정할 수 있다. 제안된 ADC는 0.13um standard CMOS 공정으로 제작되었다. 0.5V의 공급 전압을 사용하였고, 변환 범위는 rail-to-rail, 40kS/s의 샘플링 레이트에서 1.47uW의 전력을 소모한다. Figure-of-Merit(FOM)은 17.9 fJ/conversion-step이며 ENOB는 11-b 이다. A 13-b successive approximation analog-to -digital converter (ADC) is presented for ultra -low-power sensor interface. Capacitor error compensation is achieved by swapping the roles of two identical capacitor banks in DAC. The ADC is implemented in a standard 0.13‑μm CMOS. With a single supply voltage of 0.5 V and a rail-to-rail conversion range, ADC dissipates 1.47 μW at a sampling rate of 40 kS/s. It shows an FoM of 17.9 fJ/conversion-step with ENOB of 11.0-b.

300-GHz Integrated Heterodyne Receiver Chain for Phased-Array with Wide IF Bandwidth

박건우,이승종,한인수,전상근 한국과학기술원 반도체설계교육센터 2021 IDEC Journal of Integrated Circuits and Systems Vol.7 No.4

This paper presents a fully integrated terahertz receiver chain for phased-array with a wide IF bandwidth designed using a 250-nm InP double heterojunction bipolar transistor (DHBT) technology. The phased-array receiver chain consists of a variable-gain low-noise amplifier (VG-LNA), phase shifter, down-conversion mixer, and injection locking local oscillator (ILO). Each circuit block is designed to be broadband to achieve a wide receiver chain bandwidth. The VG-LNA adopts cascaded amplifying stages with a current steering technique to control the gain. While the control voltage (Vcon) varies from 2 to 3.6 V, the gain varies from 15.6 to 0 dB at 300 GHz. The noise figure is no higher than 15 dB at all Vcon conditions. The phase shifter uses a current combining structure based on Gilbert cells. The peak conversion gain is -10 dB at 303 GHz and the 3 dB bandwidth is 52 GHz extending from 270 to 322 GHz. The LO employs an injection locking technique. The locking range is from 260 to 328 GHz (22.7%) when a 10-dBm signal is injected. The maximum output power is 0.5 dBm at 300 GHz. The Gilbert-cell-based down-conversion mixer shows a 72-GHz bandwidth extending from 252 GHz to 324 GHz. The proposed fully integrated phased-array receiver chain shows a wide bandwidth characteristic. When the control voltage is set to 2.0 V, the peak conversion gain is 12.3 dB and the 3-dB bandwidth reaches 45 GHz from 270 GHz to 315 GHz.

Continuous-time delta-sigma modulator using asynchronous SAR quantizer and digital ΔΣ Truncator

신종윤,박상규 한국과학기술원 반도체설계교육센터 2018 IDEC Journal of Integrated Circuits and Systems Vol.4 No.3

As the demand for IoT related devices has increased recently, the demand for voice sensors used in these devices is increasing. Low power is a key factor because these devices have to run on batteries for long periods of time. A delta-sigma modulator is best suited for analog-to-digital converters used in the voice signal band because resolution is more important than speed. This delta sigma modulator requires a high SQNR in order to obtain high resolution, indicating that a high bit number quantizer is required. However, a high bit number quantizer requires a large number of comparators and DACs, which increases power consumption and takes up a large area. In this paper, to achieve low noise and low power dissipation, 3rd order continuous time delta-sigma (DS) ADC with a 6-bit asynchronous successive approximation register (ASAR) quantizer and a digital delta-sigma truncator which reduce a number of DACs is presented. The designed ADC front-end has been implemented through a 180 nm CMOS process and achieved 86 dB SNR and 76 dB SNDR over a 20 kHz signal band. The total chip dissipates a power of 170μW from a 1.5 V supply.

A Current-Mode Digital Controlled Buck-Boost DC-DC Converter for LED Driver

박지훈,황인철 한국과학기술원 반도체설계교육센터 2017 IDEC Journal of Integrated Circuits and Systems Vol.3 No.1

This paper presents a digital LED Driver that provides a high quality of the back light for display modules. The proposed LED driver is implemented in 0.18um CMOS process. Proposed LED driver consists of three types of circuits, a buck-boost converter, circuit for power efficiency and color reproducibility improvement and a circuit for constant current driving. The digital designed buck-boost converter improves power efficiency. To compensate for forward biased voltage of LED according to temperature, the regulator block generates a self-controlled variable reference voltage, in addition to that it also provides an optimal power efficiency of power converter. The regulator that gives a constant current to LED automatically controls the gate voltage that is needed to determine the minimum voltage headroom to prevent power deficiency. The supplying voltage of this circuit is 4.2V, 0V. Maximum operating frequency is 1MHz. Proposed LED driver can be applied to a low power chip-set projector for HD quality micro-display and in HMD also.

A 1.2V 30 MS/s SAR ADC with Foreground Capacitor Calibration

주현규,이세원,이민재 한국과학기술원 반도체설계교육센터 2019 IDEC Journal of Integrated Circuits and Systems Vol.5 No.2

– In this paper, a successive approximation register (SAR) ADC with foreground capacitor calibration is presented. In order to overcome the drawback of SAR architecture with low-power consumption, several techniques are adopted such as high-speed latch, three-stage comparator, reference-less architecture, custom metal-oxide-metal (MOM) capacitor, and foreground capacitor calibration. The design methodology and measurement procedure is presented in detail. The prototype ADC is fabricated in a 65 nm CMOS process, and it achieves signal-to-noise and distortion ratio (SNDR) over 60 dB at sampling frequency of 30 MS/s under 1.2 V supply voltage. The power consumption is 1.1 mW, and the chip area of the core ADC is 0.045 mm2.

Nonlinearity analysis of 65nm 8bit Vernier Time-to-digital Converter

고현민 한국과학기술원 반도체설계교육센터 2018 IDEC Journal of Integrated Circuits and Systems Vol.4 No.4

This paper analyzes the nonlinearity of TDC (Time-to-Digital Converter) used in wireless bearing angle measure system by using INL (Integral Non-Linearity) and DNL (Differential Non-Linearity) specification. Nonlinearity can be represented by the distance error, which indicates the uncertainty of the angle and position in this system. We investigate the distance error based on INL and cause of nonlinearity from the viewpoint of layout. We compare pre and post layout simulations of parasitic resistance in metal power line, describing important layout points to keep in mind. Jitter and mismatch simulation are proposed for setting delay buffer size and TDC time resolution. Wire bonding inductance simulation is also considered for checking robust circuit operation. Verified TDC is an 8bit with a 18ps resolution. The measured DNL and INL were 0.8 LSB and -15 LSB. Samsung 65nm process was used.

A Leakage-Tolerant 4.58µJ·ppm2 -FoMs Reconfigurable RC-to-Digital Converter for Multi-Sensor Readout

김동욱,한호영,이정협 한국과학기술원 반도체설계교육센터 2023 IDEC Journal of Integrated Circuits and Systems Vol.9 No.2

This brief presents a leakage-tolerant high-resolution reconfigurable RC-to-digital converter (R2CDC) that can readout multiple resistance/capacitance sensors using swing boosted period-modulation (SB-PM) front-end. This R2CDC employs SB-PM front-end and first-order noise shaping block that results in 23.03aF Abs. Resolution. Compared to the conventional design, the leakage current was reduced by at least 15.67 times. Implemented in a 0.18µm standard CMOS process, the proposed (R2CDC) consumes 56.38µA from a 1V supply, occupying an active area of 0.0275 mm2, achieving FoMs=4.58μJ∙ppm2, FoMw=0.359pJ/Step efficiency at a measurement time of 500µs.

A Fully-Integrated High-Voltage Generation IC for Implantable Medical Devices

송명규,차혁규 한국과학기술원 반도체설계교육센터 2019 IDEC Journal of Integrated Circuits and Systems Vol.5 No.4

This work presents the design of a fully-integrated high-voltage charge pump IC for implantable medical devices using 0.18-µm CMOS process. The implemented charge pump IC is used to generate high-voltage DC supply of around 12.8 V for the neural stimulator circuit using 3.2-V input voltage with on-chip pumping and load capacitors. The proposed hybrid charge pump IC is comprised of a feed-forward high-efficiency capacitive pumping path and an input voltage modulated feedback regulation path to maintain the output voltage with varying load current of up to 300 µA. The proposed IC achieves around 46% power efficiency at maximum current load condition.

1-1 MASH based on Pipelined-SAR ADC with a PVT Variation Robust Dynamic Amplifier

이주용,이승준,김기현,진주환,김종현,백지현,채형일 한국과학기술원 반도체설계교육센터 2021 IDEC Journal of Integrated Circuits and Systems Vol.7 No.4

Noise Shaping-Successive Approximation Register (NS-SAR) Analog-to-Digital Converters (ADCs) offer high SNDR due to low quantization noise and low comparator noise which has NS-capability. However, to achieve high SNDR, the NS-SAR needs a high bit-quantizer rather than high order NTF limited by stability. A high bit-quantizer offers smaller residue at the end of conversion. This problem is again affected by comparator noise same as SAR, although the comparator noise is shaped by given NTF. This work addresses this issue through pipelined MASH structure which allows high SNDR with a low-quantizer and a low oversampling ratio (OSR), maintaining good stability and wide bandwidth (BW). The dynamic amplifier configured in the loop filter enables high speed and low power. Our proposed ADC operates at 100 MS/s, it consumes 1.9 mW from a 1.2 V supply and achieves 86.69 dB-SNDR and 6.25 MHz-BW, when OSR is 8.