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실리콘 기판 위의 나선형 인덕터에 대한 SPICE 모델
김영석,박종욱,김남수,유현규,Kim, Yeong-Seuk,Park, Jong-Wook,Kim, Nam-Soo,Yu, Hyun-Kyu 대한전자공학회 2000 電子工學會論文誌-SD (Semiconductor and devices) Vol.37 No.10
회로설계 엔지니어들이 쉽게 RF IC 설계에 사용할 수 있는 나선형 인덕터의 SPICE 모델을 개발하였다. 이 모델은 나선형 인덕터의 등가회로 소자 값들을 SPICE의 user-defined function 및 subcircuit 기능을 이용하여, 레이아웃 변수, 공정 변수, 실리콘 기판 변수로부터 정의하였다. 특히 인덕턴스는 임의의 회전에 대한 인덕턴스 Li 및 임의의 두 회전에 대한 상호 인덕턴스 Mij를 subcircuit으로 정의하여 전체 인덕턴스 값을 계산하였다. 모델의 정확성을 검증하기 위하여 CMOS 0.8${\mu}m$ 공정으로 제작된 나선형 인덕터의 측정 s-파라미터, 총 인덕턴스 및 quality-factor 결과를 시뮬레이션 데이터와 비교한 결과 일치함을 확인하였다. 본 논문에서 제시된 SPICE를 이용한 나선형 인덕턴스 모델은 scalable하며, 실리콘 기판의 영향등을 포함하기 때문에 레이아웃 최적화에 쉽게 사용할 수 있는 장점을 가진다. The SPICE model of the spiral inductor on silicon substrate which can be easily used for the RF IC design has been developed. In this proposed model the equivalent circuit element of the spiral inductor are defined by the layout and process parameters using the user-defined function and subcircuit of the SPICE. The total inductance is calculated using the subcircuit Li for the arbitrary turn i and the subcircuit Mij for two arbitrary turns. The model was verified by comparing the simulated data with the measured s-parameters, total inductance, and quality factor of the spiral inductor fabricated by the CMOS 0.8${\mu}m$ process. The proposed SPICE model of the spiral inductor is scalable and includes the effects of the silicon substrate.
최성열,김영석,Choi, Seong-Yeol,Kim, Yeong-Seuk 한국정보통신학회 2018 한국정보통신학회논문지 Vol.22 No.7
본 논문에서는 셀프-캐스코드 구조를 이용한 LDO 레귤레이터를 제안하였다. 셀프-캐스코드 구조의 소스 측 MOSFET의 채널 길이를 조절하고, 드레인 측 MOSFET의 바디에 순방향 전압을 인가함으로써 최적화하였다. 오차 증폭기 입력 차동단의 셀프-캐스코드 구조는 높은 트랜스컨덕턴스를 가지도록, 출력단은 높은 출력 저항을 가지도록 최적화하였다. 제안 된 LDO 레귤레이터는 $0.18{\mu}m$ CMOS 공정을 사용하였고, SPECTERE를 이용하여 시뮬레이션 되었다. 제안 된 셀프-캐스코드 구조를 이용한 LDO 레귤레이터의 로드 레귤레이션은 0.03V/A로 기존 LDO의 0.29V/A보다 급격하게 개선되었다. 라인 레귤레이션은 2.23mV/V로 기존 회로보다 약 3배 향상되었다. 안정화 속도는 625ns로 기존 회로보다 346ns 개선되었다. This paper proposes a low-dropout voltage regulator(LDO) using self-cascode structure. The self-cascode structure was optimized by adjusting the channel length of the source-side MOSFET and applying a forward voltage to the body of the drain-side MOSFET. The self-cascode of the input differential stage of the error amplifier is optimized to give higher transconductance, but the self-cascode of the output stage is optimized to give higher output resistance, The proposed LDO using self-cascode structure was designed by a $0.18{\mu}m$ CMOS technology and simulated using SPECTRE. The load regulation of the proposed LDO regulator was 0.03V/A, whereas that of the conventional LDO was 0.29V/A. The line regulation of the proposed LDO regulator was 2.23mV/V, which is approximately three times improvement compared to that of the conventional LDO. The transient response of the proposed LDO regulator was 625ns, which is 346ns faster than that of the conventional LDO.
다중 표준 시스템을 위한 이득 곡선 제어기를 가진 가변이득 증폭기 설계
최문호,이원영,김영석,Choi, Moon-Ho,Lee, Won-Young,Kim, Yeong-Seuk 한국전기전자재료학회 2008 전기전자재료학회논문지 Vol.21 No.4
In this paper, variable gain amplifier(VGA) with a gain slope controller has been proposed and verified by circuit simulations and measurements. The proposed VGA has a gain control, gain slope switch and variable gain range. The input source coupled pair with diode connected load is used for VGA gain stage. The gain slope controller with switch can control VGA gain slope. The proposed VGA is fabricated in $0.18{\mu}m$ CMOS process for multi -standard wireless receiver. The proposed two stage VGA consumes min. 2.0 mW to max. 2.6 mW in gain control range and gives input IP3 of -3.77 dBm and NF of 28.7 dB at 1.8 V power supply under -25 dBm, 1 MHz input. The proposed VGA has 37 dB(-16 dB $\sim$ 21 dB) variable gain range, and 8 dB gain range control per 0.3 V control voltage, and can provide variable gain, positive and negative gain slope control, and gain range control. This VGA characteristics provide design flexibility in multi-standard wireless receiver.
전원전압 1.0V 산소 및 과산화수소 기반의 정전압분극장치 설계
김재덕,최성열,김영석,Kim, Jea-Duck,XIAOLEI, ZHONG,Choi, Seong-Yeol,Kim, Yeong-Seuk 한국정보통신학회 2017 한국정보통신학회논문지 Vol.21 No.2
본 논문에서는 전원전압 1V에서 동작하는 산소 및 과산화수소 기반의 혈당전류를 측정할 수 있는 통합형 정전압분극장치를 설계하고 제작하였다. 정전압분극장치는 저전압 OTA, 캐스코드 전류거울 그리고 모드 선택회로로 구성되어 있다. 정전압분극장치는 산소 및 과산화수소 기반에서 혈당의 화학반응으로 발생하는 전류를 측정할 수 있다. OTA의 PMOS 차동 입력단의 바디에는 순방향전압을 인가하여 문턱전압을 낮추어 낮은 전원전압이 가능하도록 하였다. 또한 채널길이변조효과로 인한 전류의 오차를 줄이기 위해 캐스코드 전류거울이 사용되었다. 제안한 저전압 정전압분극장치는 Cadence SPECTRE를 이용하여 설계하였으며, 매그나칩 $0.18{\mu}m$ CMOS 공정을 이용하여 제작되었으며 회로의 크기는 $110{\mu}m{\times}60{\mu}m$이다. 전원전압 1.0V에서 소모전류는 최대 $46{\mu}A$이다. 페리시안화칼륨($K_3Fe(CN)_6$)을 사용하여 제작된 정전압분극장치의 성능을 확인하였다. In this paper, a unified potentiostat which can measure the current of both $O_2$-based and $H_2O_2$-based blood glucose sensors with low supply voltage of 1.0V has been designed and verified by simulations and measurements. Potentiostat is composed of low-voltage operational transconductance amplifier, cascode current mirrors and mode-selection circuits. It can measure currents of blood glucose chemical reactions occurred by $O_2$ or $H_2O_2$. The body of PMOS input differentional stage of the operational transconductance amplifier is forward-biased to reduce the threshold voltage for low supply voltage operation. Also, cascode current mirror is used to reduce current measurement error generated by channel length modulation effects. The proposed low-voltage potentiostat is designed and simulated using Cadence SPECTRE and fabricated in Magnachip 0.18um CMOS technology with chip size of $110{\mu}m{\times}60{\mu}m$. The measurement results show that consumption current is maximum $46{\mu}A$ at supply voltage of 1.0V. Using the persian potassium($K_3Fe(CN)_6$) equivalent to glucose, the operation of the fabricated potentiostat was confirmed.
Neutralization을 이용한 주파수 변환기 설계
최문호,최원호,김영석,Choi, Moon-Ho,Choi, Won-Ho,Kim, Yeong-Seuk 한국전기전자재료학회 2008 전기전자재료학회논문지 Vol.21 No.4
In this paper, a 2.4 GHz low-voltage CMOS double-balanced down-conversion mixer using neutralization technique has been proposed and verified by circuit simulations and measurements. The grounded source structure was used for low-voltage operation. The neutralization technique was used to improve a conversion gain. The proposed mixer is fabricated in $0.25{\mu}m$ CMOS process for a 2.4 GHz wireless receiver. The mixer consumes 1.94 mW and gives conversion gain of 5.66 dB, input IP3 of 0.7 dBm and P1dB of -11.2 dBm at 1.5 V power supply. Measured results for the designed mixer show improved conversion gain of 2.86 dB over conventional mixer of grounded source structure.
낮은 전원전압 민감도를 가지는 셀프 캐스코드 구조를 이용한 밴드갭 레퍼런스
ZHONG XIAOLEI,김영석(Yeong-Seuk Kim) 대한전자공학회 2015 대한전자공학회 학술대회 Vol.2015 No.11
Bandgap voltage reference circuits, used in battery-operated portable equipments should be able to be designed using standard digital CMOS process and present low-power operation. In this paper a CMOS bandgap voltage reference using self-cascode MOSFET is designed. Self-cascode bandgap voltage reference was utilized by 0.18um CMOS technology and simulated by Cadence Specter. Its temperature coefficient(TC) is typically 29.70ppm/℃ in the temperature of -25℃ to 100℃ and its output resistance of optimized self-cascode bandgap voltage reference is nearly 225MΩ.
이중 일함수 구조를 적용한 N-채널 EDMOS 소자의 항복전압 및 온-저항 특성
김민선,백기주,김영석,나기열,Kim, Min-Sun,Baek, Ki-Ju,Kim, Yeong-Seuk,Na, Kee-Yeol 한국전기전자재료학회 2012 전기전자재료학회논문지 Vol.25 No.9
In this paper, TCAD assessment of 30-V class n-channel EDMOS (extended drain metal-oxide-semiconductor) transistors with DWFG (dual work function gate) structure are described. Gate of the DWFG EDMOS transistor is composed of both p- and n-type doped region on source and drain side. Additionally, lengths of p- and n-type doped gate region are varied while keeping physical channel length. Two-dimensional device structures are generated trough TSUPREM-4 and their electrical characteristics are investigated with MEDICI. The DWFG EDMOS transistor shows improved electrical characteristics than conventional device - i.e. higher transconductance ($g_m$), better drain output current ($I_{ON}$), reduced specific on-resistances ($R_{ON}$) and higher breakdown characteristics ($BV_{DSS}$).
Native-V<sub>th</sub> MOSFET을 이용한 셀프-캐스코드 구조의 아날로그 성능 분석
이대환,백기주,하지훈,나기열,김영석,Lee, Dae-Hwan,Baek, Ki-Ju,Ha, Ji-Hoon,Na, Kee-Yeol,Kim, Yeong-Seuk 한국전기전자재료학회 2013 전기전자재료학회논문지 Vol.26 No.8
The self-cascode (SC) structure has low output voltage swing and high output resistance. In order to implement a simple and better SC structure, the native-$V_{th}$ MOSFETs which has low threshold voltage($V_{th}$) is applied. The proposed SC structure is designed using a qualified industry standard $0.18-{\mu}m$ CMOS technology. Measurement results show that the proposed SC structure has higher transconductance as well as output resistance than single MOSFET. In addition, analog building blocks (e.g. current mirror, basic amplifier circuits) with the proposed SC structure are investigated using by Cadence Spectre simulator. Simulation results show improved electrical performances.