Performance Optimization of LDMOS Transistor with Dual Gate Oxide for Mixed-Signal Applications

백기주,나기열,김영석 한국전기전자재료학회 2015 Transactions on Electrical and Electronic Material Vol.16 No.5

This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide- semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (RON) and 50% drain conductance (gds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.

Growth and Differentiation of Mammary Epithelial Cells in Extracellular Maxtrix Culture

백기주,윤정현,김동염,전성실,양한석,김남득,Paik, Kee-Joo,Yoon, Jeong-Hyun,Kim, Dong-Yeom,Jeon, Seong-Shil,Yang, Han-Suk,Kim, Nam Deuk Korean Society of Life Science 1995 생명과학회지 Vol.5 No.1

Mammary orgamoids(ductal and endbud fragments) were cultured in a complete hormone medium(CHM) with 10%FBS, estradiol, progesterone, hydrocortisone, insulin, and prolactin, Several types of colonies were observed: stellate(14$$\pm$5.5%), duct(41$\pm$5.6%), web(35$\pm$3.6%), squamous(6$\pm$2.1%), and lobuloduct(4$\pm$1.2%), Squamous colony was typical squamous metaplasia(SM) with several layers of squamous epithlia and keratin pearls. At the immunocytochemical study, casein proteins were predominantly localized near the apical surfaces of the cells or in the lumina of ductal or lobuloductal colonies. To inhibit the formation of SM, we treated organoids with all-trans retinoic acid(RA) from 10$^{-6}$ to 10$^{-17}$ M in CHM. Formation of SN was completely inhibited at 10$^{-9}$M RA in CHM. The frequency of lobuloductal colony formation was increased with the augmentation of RA concentration.

미학과 예술학

백기주 일념 1993 교수아카데미총서 Vol.6 No.-

더 말할 나위 없이 미나 예술은 인간생활에서 유리된, 인연이 먼 추상관념이 아니라, 구체적 현상으로서 끊임없이 바로 우리의 일상적인 생활주변에서 우리의 마음 속 깊이 스며들어 우리에게 즐거움과 기쁨을 안겨 주며, 우리의 생을 윤택하고 충실하고 행복하게 해 주는 존귀한 실재요, 일면 불가사의하고도 신비스러운 힘을 가진 소중한 존재이다. 그런데 우리는 인생에 있어서 미나 예술의 가치를 깊이 인식하고는 있으면서도, 일단 그 본질이나 의미를 묻게 되면 흔히 당황하게 되는 경우를 보게 된다. 이는 미나 예술이란 것이 그처럼 불가사의하고도 신비스러운 것인 까닭으로 그것은 오직 직감으로 감득되어야 하는 것일 뿐이지, 그 이해는 불필요한 것이라는 견해 때문이다. 그러나 이는 미나 예술이 간직하고 있는 신비성으로 인한 필연적 결과일 뿐이다. 신비스러운 미적 활동 내지 예술활동 그 자체와 한편 이에 관해서 학리상 탐구하며 이해하려는 활동과는 문제가 다르다.

Self-Cascode Structures Using Optional devices in Standard CMOS Technology

백기주,나기열,김영석 한국과학기술원 반도체설계교육센터 2016 IDEC Journal of Integrated Circuits and Systems Vol.2 No.1

This paper describes two possible configurations of an asymmetric-VTH self-cascode (SC) structure using optional devices in a 0.18-μm standard CMOS process. Standard CMOS technologies offer optional devices for a range of circuit design solutions, such as zero threshold voltage (ZVT) MOSFETs and thick gate oxide input/output (I/O) MOSFETs. In this paper, ZVT and I/O MOSFETs were implemented in the asymmetric-threshold voltage (VTH) self-cascode (SC) structures. These asymmetric-VTH SC structures with optional devices and a two-stage operational amplifier (OPAMP) using these SC structures were fabricated and evaluated. As a result of single device level evaluation, the SC with ZVT MNOSFET device showed improved output resistance as well as transconductance than the conventional single MOSFETs. From measurements of the fabricated two-stage OPAMP, the OPAMP with ZVT-SC device showed higher DC gain, faster slew rate, and higher unity-gain frequency.

Suppression Techniques of Subthreshold Hump Effect for High-Voltage MOSFET

백기주,나기열,박정현,김영석 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.5

In this paper, simple but very effectivetechniques to suppress subthreshold hump effect forhigh-voltage (HV) complementary metal-oxidesemiconductor(CMOS) technology are presented. Two methods are proposed to suppress subthresholdhump effect using a simple layout modificationapproach. First, the uniform gate oxide method isbased on the concept of an H-shaped gate layoutdesign. Second, the gate work function controlmethod is accomplished by local ion implantation. Forour experiments, 0.18 μm 20 V class HV CMOStechnology is applied for HV MOSFETs fabrication. From the measurements, both proposed methods arevery effective for elimination of the inverse narrowwidth effect (INWE) as well as the subthreshold hump

VDT작업자의 자각증상에 영향을 미치는 요인

이중근,이연수,노재훈,박계열,백기주 大韓産業醫學會 1997 대한직업환경의학회지 Vol.9 No.1

In order to investigate symptoms prevalence related to visual display terminal(VDT) syndrome, and to evaluate the variables affecting the development of the VDT syndrome, a questionnaire survey was conducted on 119(92 men and 27 women) VDT operators who had been engaged in one plant design company in seoul. The results were as follows : The average age of questionnaire respondents was 30. The average years of service were 4.3 years, and the working hours per day with VDT for half of them were more than 4 hours with the average being about 4.7 hours. The majority of subjects(71 persons) were working at computer aided design(CAD) or computer programming tasks. Subjective symptoms of VDT syndrome were divided into 4 groups with musculoskeletal, eye, skin, and industrial fatigue according to their major affected organ. A high incidence of complaints of eye discomfort was observed. In the 3 subgroups of industrial fatigue symptom, the highest average group score was accounted for by 'dullness and sleepiness', followed by 'difficulty in concentration', 'bodily projection of fatigue' in the order of sequence, suggesting the heavier mental stress of VDT work rather than physical burden. Relationship among these 4 groups of symptoms showed statistically significant correlations one another. This result suggests that VDT syndrome is a multi-organ disease composed of these 4 symptom groups which were commonly caused by the use of VDT. Multiple regression analysis were used to examine the relationship between risk factors and these symptom groups of VDT syndrome. As the result of analysis, the most important risk factor for VDT syndrome was the average daily VDT working hours. The longer was VDT working hours, the higher was symptom prevalence of VDT syndrome. In addition, daily total working hours including VDT working hours and shift of work also affected the health of VDT users. In order to protect workers from VDT syndrome, it is urgently required to implement standard management recommendations including restriction of VDT working hours and allowance of more sufficient resting time for VDT workers.

이중 일함수 구조를 적용한 N-채널 EDMOS 소자의 항복전압 및 온-저항 특성

김민선,백기주,김영석,나기열,Kim, Min-Sun,Baek, Ki-Ju,Kim, Yeong-Seuk,Na, Kee-Yeol 한국전기전자재료학회 2012 전기전자재료학회논문지 Vol.25 No.9

In this paper, TCAD assessment of 30-V class n-channel EDMOS (extended drain metal-oxide-semiconductor) transistors with DWFG (dual work function gate) structure are described. Gate of the DWFG EDMOS transistor is composed of both p- and n-type doped region on source and drain side. Additionally, lengths of p- and n-type doped gate region are varied while keeping physical channel length. Two-dimensional device structures are generated trough TSUPREM-4 and their electrical characteristics are investigated with MEDICI. The DWFG EDMOS transistor shows improved electrical characteristics than conventional device - i.e. higher transconductance ($g_m$), better drain output current ($I_{ON}$), reduced specific on-resistances ($R_{ON}$) and higher breakdown characteristics ($BV_{DSS}$).

OPAMP Design Using Optimized Self-Cascode Structures

김형순,백기주,이대환,김영석,나기열 한국전기전자재료학회 2014 Transactions on Electrical and Electronic Material Vol.15 No.3

A new CMOS analog design methodology using an independently optimized self-cascode (SC) is proposed. Thisidea is based on the concept of the dual-workfunction-gate MOSFETs, which are equivalent to SC structures. Thechannel length of the source-side MOSFET is optimized, to give higher transconductance (gm) and output resistance(rout). The highest gm and rout of the SC structures are obtained by independently optimizing the channel length ratioof the SC MOSFETs, which is a critical design parameter. An operational amplifier (OPAMP) with the proposeddesign methodology using a standard digital 0.18-μm CMOS technology was designed and fabricated, to providebetter performance. Independently gm and rout optimized SC MOSFETs were used in the differential input and outputstages, respectively. The measured DC gain of the fabricated OPAMP with the proposed design methodology wasapproximately 18 dB higher, than that of the conventional OPAMP.

아날로그 응용을 위한 DWFG MOSFET의 매크로 모델 및 연산증폭기 설계

하지훈,백기주,이대환,나기열,김영석,Ha, Ji-Hoon,Baek, Ki-Ju,Lee, Dae-Hwan,Na, Kee-Yeol,Kim, Yeong-Seuk 한국전기전자재료학회 2013 전기전자재료학회논문지 Vol.26 No.8

In this paper, a simple macro model of n-channel MOSFET with dual workfunction gate (DWFG) structure is proposed. The DWFG MOSFET has higher transconductance and lower drain conductance than conventional MOSFET. Thus analog circuit design using the DWFG MOSFET can improve circuit characteristics. Currently, device models of the DWFG MOSFET are insufficient, so simple series connected two MOSFET model is proposed. In addition, a two stage operational amplifier using the proposed DWFG MOSFET macro model is designed to verify the model.

Native-V_th MOSFET을 이용한 셀프-캐스코드 구조의 아날로그 성능 분석

이대환,백기주,하지훈,나기열,김영석,Lee, Dae-Hwan,Baek, Ki-Ju,Ha, Ji-Hoon,Na, Kee-Yeol,Kim, Yeong-Seuk 한국전기전자재료학회 2013 전기전자재료학회논문지 Vol.26 No.8

The self-cascode (SC) structure has low output voltage swing and high output resistance. In order to implement a simple and better SC structure, the native-$V_{th}$ MOSFETs which has low threshold voltage($V_{th}$) is applied. The proposed SC structure is designed using a qualified industry standard $0.18-{\mu}m$ CMOS technology. Measurement results show that the proposed SC structure has higher transconductance as well as output resistance than single MOSFET. In addition, analog building blocks (e.g. current mirror, basic amplifier circuits) with the proposed SC structure are investigated using by Cadence Spectre simulator. Simulation results show improved electrical performances.