Dynamic response of an overhead transmission tower–line system to high-speed train-induced wind

Meng Zhang,Ying Liu,Hao Liu,Guifeng Zhao 한국풍공학회 2022 Wind and Structures, An International Journal (WAS Vol.34 No.4

The current work numerically investigates the transient force and dynamic response of an overhead transmission tower–line structure caused by the passage of a high-speed train (HST). Taking the CRH2C HST and an overhead transmission tower–line structure as the research objects, both an HST–transmission line fluid numerical model and a transmission tower–line structure finite element model are established and validated through comparison with experimental and theoretical data. The transient force and typical dynamic response of the overhead transmission tower–line structure due to HST-induced wind are analyzed. The results show that when the train passes through the overhead transmission tower–line structure, the extreme force on the transmission line is related to the train speed with a significant quadratic function relationship. Once the relative distance from the track is more than 15 m, the train-induced force is small enough to be ignored. The extreme value of the mid-span dynamic response of the transmission line is related to the train speed and span length with a significant linear functional relationship.

Pilot Symbol Assisted High Speed Packet Transmission System based on Adaptive OFDM in Broadband Mobile Channel

Ahn, Chang-Jun,Sasase, Iwao The Korea Institute of Information and Commucation 2003 Journal of communications and networks Vol.5 No.1

4G mobile communication system requires the throughput of 10-100Mbps. Adaptive modulated OFDM system is promising technique for increasing the throughput. In the pilot symbol assisted high-speed packet transmission system, the data symbol duration is generally considered to be small compared to the coherence time. However, OFDM symbol duration is longer than the symbol duration of a single carrier system, so that the packet duration of the pilot symbol assisted high speed packet transmission system is long. In this case, the change of channel conditions is too fast to be accurately estimated by channel estimator at the receiver in high Doppler frequency, so that many errors occur during demodulation, especially with the data symbols at the end of each packet. In this paper, we consider the BER at various instantaneous $E_b/N_o$ that includes the demodulation errors in high Doppler frequency. When the coherence time is ten times longer than the duration of a single packet, the channel can be closely approximated as an AWGN channel. Otherwise, the approximation breaks down and the above-mentioned errors that occur during demodulation must be taken into consideration. In this paper, we propose the pilot symbol assisted high speed packet transmission system based on adaptive OFDM using a novel lookup table to consider the demodulated errors and evaluate the throughput performance.

3상 대용량 무선 전력 전송 시스템

오정식,이명진,차승태,김주용,이광운,박태식,Oh, Jungsik,Lee, Myungjin,Cha, Seungtae,Kim, Juyoung,Lee, Kwangwoon,Park, Taesik 한국전기전자학회 2017 전기전자학회논문지 Vol.21 No.3

대용량 무선 전력 전송 시스템은 ESS, 배터리 장치 등의 발전을 위한 핵심 기술이다. 무선 전력 전송 장치는 현재 자기유도 및 자기공진 기술들이 주를 이루고 있으며 유선 전력 전송에 비해 전력 전송 용량이 낮고 효율이 낮은 단점이 있다. 이 논문에서는 자기 결합을 갖는 가변속 모터 시스템을 기반으로 하는 대용량 무선 전력 전송 시스템을 제안하고자 한다. 제안된 방식은 대용량 전력 전송이 가능하며, 고효율과 낮은 고장 가능성의 장점을 가지고 있으며 시뮬레이션과 실험을 통해 제안된 기법의 성능을 검증하였다. High-power wireless transmission system becomes a key technology for the advance of battery-powered devices. The wireless power transfer devices are currently dominated by the inductive and capacitive wireless power transfer systems, which have relatively low power transmission capacity and low efficiency rather than the wired power transmission. The work presented in this paper proposes an alternative method of high-power transmission system, based on a variable speed motor system with a magnetic coupling. It enables high-capacity power transmission, high efficiency, and low possibility of failures, and the performance of the proposed scheme is verified by simulation and experiments.

고속 무선 전송을 위한 QPSK 복조기 FPGA 설계

정지원 한국전자파학회 2003 한국전자파학회논문지 Vol.14 No.12

본 논문에서는 QPSK 방식을 채용하는 고속 무선 전송 시스템에 적용될 수 있는 Zero-Crossing IF-level QPSK 복조기에 대해서, 복조기에 소요되는 알고리즘들을 고찰하고 이를 구현하기 위한 H/W구조에 대해서 언급한다. Zero-Crossing IF-level QPSK 복조기를 구현하기 위해서, 비트 동기를 포착하는 심볼 동기부와 반송파 동기를 포착하는 반송파 동기부가 구현되어야 하는데, 심볼 동기부로는 Gardner 알고리즘을, 반송파 동기부로는 빠른 반송파 포착을 위한 Decision-Directed 동기화 알고리즘을 적용하여 설계, 구현하였다. 설계한 QPSK복조기를 Altera 사의 Design Compiler를 이용하여 CPLD-FLEX10K 칩에 합성해 본 결과 약 2.6 Mbps의 전송속도까지 복조 가능하였다. 설계된 Zero-Crossing IF-level QPSK 복조기를 ASIC으로 구현할 경우 CPLD속도의 5∼6 이상 고속화가 가능하므로 약 10 Mbps급 Zero-Crossing IF-level QPSK 복조가 가능하다. High-speed QPSK demodulator has been one important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes Zero-Crossing IF-level(ZCIF) QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. ZCIF QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tracking to fabricate FPGA chip. The testing results of the implemented onto CPLD-FLEX10K chip show demodulation speed is reached up to 2.6[Mbps]. Actually in case of designing by ASIC, its speed may be faster than CPLD by 5 times. Therefore, it is possible to fabricate the ZCIF QPSK demodulator with speed of 10 Mbps.

Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY Interface

Seong, Ki-Hwan,Lim, Ji-Hoon,Kim, Byungsub,Sim, Jae-Yoon,Park, Hong-June The Institute of Electronics and Information Engin 2014 Journal of semiconductor technology and science Vol.14 No.4

A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of transmission line in SPICE model is converted into that in Verilog model by converting the full-scale analog signal into an 11-bit digital code after uniform time sampling. The receiver waveform of transmission line is calculated by adding or subtracting the single-pulse response in Verilog model depending on the transmitting digital code values with appropriate time delay. The application of this work to a USB 2.0 high-speed PHY interface reduces the simulation time to less than three minutes with error less than 5% while the mixed-mode simulation takes more than two days for the same circuit.

Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY Interface

성기환,이지훈,김병섭,심재윤,박홍준 대한전자공학회 2014 Journal of semiconductor technology and science Vol.14 No.4

A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of transmission line in SPICE model is converted into that in Verilog model by converting the full-scale analog signal into an 11-bit digital code after uniform time sampling. The receiver waveform of transmission line is calculated by adding or subtracting the single-pulse response in Verilog model depending on the transmitting digital code values with appropriate time delay. The application of this work to a USB 2.0 high-speed PHY interface reduces the simulation time to less than three minutes with error less than 5% while the mixed-mode simulation takes more than two days for the same circuit.

Analysis and Design Optimization of Interconnects for High-Speed LVDS Applications

류지열,노석호,Ryu, Jee-Youl,Noh, Seok-Ho The Institute of Electronics and Information Engin 2009 電子工學會論文誌-CI (Computer and Information) Vol.46 No.10

This paper addresses the analysis and the design optimization of differential interconnects for high-speed Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and trace space in differential printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, and time-domain transient simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects. We believe that the proposed approach is very helpful to optimize high-speed differential FPCB interconnects for LVDS applications. 본 논문에서는 고속 저전압 차동 신호(Low-Voltage Differential Signaling, LVDS) 전송방식의 응용을 위한 전송선 분석 및 설계 최적화 방법을 제안한다. 차동 전송 경로 및 저전압 스윙 방법의 발전으로 인해 저전압 차동 신호 전송방식은 데이터 통신 분야, 고 해상도 디스플레이 분야, 평판 디스플레이 분야에서 매우 적은 소비전력, 개선된 잡음 특성 및 고속 데이터 전송률을 제공한다. 본 논문은 차동 유연성 인쇄 회로 보드(flexible printed circuit board, FPCB) 전송선에서 선 폭, 선 두께 및 선간격과 같은 전송선 설계 변수들의 최적화 기법을 이용하여 직렬 접속된 전송선에서 발생하는 임피던스 부정합과 신호 왜곡을 감소시키기 위해 개선 모델과 개발된 수식을 제안한다. 이러한 차동 FPCB 전송선의 고주파 특성을 평가하기 위해 주파수 영역에서 전파(full-wave) 전자기 시뮬레이션 및 시간 영역 시뮬레이션을 각각 수행하였다. 본 논문에서 제안하는 방법은 저전압 차동 신호 방식의 응용을 위한 고속 차동 FPCB 전송선을 최적화하는데 매우 도움이 되리라 믿는다.

테라급 스위치 패브릭 인터페이스를 위한 고속 신호 전송로의 성능 분석

최창호(Chang-ho CHOI),김환우(Whan-woo KIM) 대한전자공학회 2014 전자공학회논문지 Vol.51 No.12

고속 전송로를 위한 PCB(Printed Circuit Board) 설계기술은 꾸준히 발전되고 있으며, 통신 시스템의 대용량화에 맞추어 백플레인(Backplane)에 사용되는 스위치 패브릭 인터페이스(Switch Fabric Interface) 또한 10Gbps 이상의 직렬 인터페이스(Serial Interface)를 사용하도록 표준화가 진행되고 있다. 본 논문에서는 테라급 시스템에서 스위치 패브릭 인터페이스로 11.5Gbps의 직렬링크를 사용하기 위하여, PCB 재질 따른 전송로의 전송거리 별 성능을 비교하고, 비아 스터브(Via Stub)의 길이에 의한 영향 및 누화현상(Crosstalk)에 의한 영향을 시뮬레이션을 수행하여 분석하였다. 시뮬레이션의 결과로 백플레인 보드에 저유전 재질 PCB를 사용함으로써, 전송손실에서 8㏈의 개선효과를 얻어 표준에서 정한 ?25㏈ 기준을 만족하는 것을 확인하였다. 또한 비아 스터브 길이에 의한 반사손실의 영향을 분석하여 백드릴(Back-drill)여부를 결정하였으며, 전송신호 간 상호간섭을 최소화하는 이격거리를 검증하였다. 이러한 시뮬레이션의 결과로부터 모든 스위치 패브릭 링크에 11.5Gbps의 직렬링크를 적용할 수 있도록 가장 효율적인 시스템구조를 확정하였다. PCB design technology for high-speed transmission line has been developed continuously. Adapting to the high capacity of the communication system, switch fabric interface used for backplane is being standardized to accommodate more than 10Gbps serial interface. In this paper, various computer simulations are performed to compare the performance of each transmission line per length according to PCB material, and also to analyze the effect from via stub length and crosstalk, for the purpose of applying 11.5Gbps serial interface as a switch fabric interface in tera-bit switching system. As a result of the simulation, important design issues, such as PCB material of each board supporting 8㏈ improvement in transmission loss using low loss PCB, maximum available stub length on transmission line via, whether or not to apply the backdrill process to the via, and the clearance of the differential pair between transmission lines, are determined. The most efficient system architecture which could be applied 11.5Gbps serial interface in all switch fabric interfaces is defined from the simulation results.

Enhancement of recovery stresses of the Ni-50.2Ti alloy by severe plastic deformation using a high-ratio differential speed rolling technique

Lim, Y.G.,Han, S.H.,Choi, E.S.,Kim, W.J. Pergamon 2016 Scripta materialia Vol.124 No.-

The Ni-50.2Ti alloy was severely plastically deformed by differential speed rolling with high speed ratios in range of 2-4.2. The maximum recovery and residual recovery stresses, which are important for applications in civil engineering, were improved after rolling. This result was attributed to the significant increase in the strength of the martensite phase and the large decrease in martensitic transformation finish temperature (M<SUB>f</SUB>) by microstructural refinement. Post-deformation annealing at 673K deteriorated the shape memory properties, which was attributed to the formation of a martensitic R-phase in the alloy and an increase in the M<SUB>f</SUB> temperature.

Time-Slotted Scheduling Schemes for Multi-hop Concurrent Transmission in WPANs with Directional Antenna

Muhammad Bilal Khan,강문수,Shah Sayed Chhattan,강신각 한국전자통신연구원 2014 ETRI Journal Vol.36 No.3

To achieve high-speed (giga-bit) connectivity for shortrangewireless multimedia applications, the millimeterwave(mmWave) wireless personal area networks withdirectional antennas are gaining increased interest. Due tothe use of directional antennas and mmWavecommunications, the probability of non-interferingtransmissions increases in a localized region. Networkthroughput can be increased immensely by the concurrenttime allocation of non-interfering transmissions. Theproblem of finding optimum time allocation for concurrenttransmissions is an NP-hard problem. In this paper, wepropose two enhanced versions of previously proposedmulti-hop concurrent transmission (MHCT) schemes. Toincrease network capacity, the proposed schemes efficientlymake use of the free holes in the time-allocation map of theMHCT scheme; thus, making it more compact.