The Effects of Boron Passivation and Re-Oxidation on the Properties of the 4H-SiC/SiO_2 Interface

정충부,김광수 한국물리학회 2019 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.74 No.7

We investigated the effect of boron passivation and re-oxidation on the properties of the silicon carbide/silicon dioxide interface. Metal-oxide-semiconductor capacitors were fabricated on 4H-silicon carbide substrates and the capacitance-voltage properties were measured. The high-low capacitance-voltage method was used to obtain the interface trap density from the capacitance-voltage curve. Boron passivation is known to be effective in reducing the size of carbon clusters at the silicon-carbide/silicon-dioxide interface. Also re-oxidation is known to be effective in improving the quality of the oxide and reducing the dangling bond set of the silicon-carbide/silicon-dioxide interface. The effect of each boron passivation and re-oxidation method on the silicon carbide/silicon dioxide interface was analyzed by observing the interface trap density obtained from the capacitance-voltage curves. We found that the interface trap density could be significantly improved; the best sample exhibited an interface trap density approximately 51% lower than that of the sample subjected to conventional oxidation via wet oxidation, boron passivation and wet re-oxidation. The interface of each sample was investigated with X-ray photoelectron spectroscopy, based on which we inferred that boron-passivation reduced the size of residue carbon clusters located at the silicon-carbide/silicon-dioxide interface.

GaN Schottky Barrier MOSFET의 출력 전류에 대한 계면 트랩의 영향

박병준,함성호,김한솔 한국센서학회 2022 센서학회지 Vol.31 No.4

We analyzed the effects of the interface trap on the output characteristics of an inversion mode n-channel GaN Schottky barrier (SB)-MOSFET based on the Nit distribution using TCAD simulation. As interface trap number density (Nit) increased, the threshold voltageincreased while the drain current density decreased. Under Nit=5.0×1010 cm-2 condition, the threshold voltage was 3.2 V for VDS=1 V,and the drain current density reduced to 2.4 mA/mm relative to the non-trap condition. Regardless of the Nit distribution type, there wasan increase in the subthreshold swing (SS) following an increase in Nit. Under U-shaped Nit distribution, it was confirmed that the SSvaried depending on the gate voltage. The interface fixed charge (Qf) caused an shift in the threshold voltage and increased the off-statecurrent collectively with the surface trap. In summary, GaN SB-MOSFET can be a building block for high power UV optoelectroniccircuit provided the surface state is significantly reduced.

Improved Conductance Method for Determining Interface Trap Density of Metal–Oxide–Semiconductor Device with High Series Resistance

Yang, Hyundoek,Son, Yunik,Choi, Sangmoo,Hwang, Hyunsang The Japan Society of Applied Physics 2005 Japanese journal of applied physics Vol.44 No.46

<P>The existence of series resistance in metal–oxide–semiconductor (MOS) devices can result in both the degradation of capacitance at a high frequency and the decrease in conductance. Using a conventional conductance method that does not consider the series resistance, the interface trap density can be underestimated. We propose an improved conductance method based on an equivalent circuit model including the series resistance. Compared with the conventional method, this new method enables the accurate determination of interface trap density.</P>

저온 다결정 실리콘 박막 트랜지스터의 비정상적인 Hump 현상 분석

김유미,정광석,윤호진,양승동,이상율,이희덕,이가원,Kim, Yu-Mi,Jeong, Kwang-Seok,Yun, Ho-Jin,Yang, Seung-Dong,Lee, Sang-Youl,Lee, Hi-Deok,Lee, Ga-Won 한국전기전자재료학회 2011 전기전자재료학회논문지 Vol.24 No.11

In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density ($D_{it}$) and grain boundary trap density ($N_{trap}$) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.

Tunable Mobility in Double-Gated MoTe₂ Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites

Ji, Hyunjin,Joo, Min-Kyu,Yi, Hojoon,Choi, Homin,Gul, Hamza Zad,Ghimire, Mohan Kumar,Lim, Seong Chu American Chemical Society 2017 ACS APPLIED MATERIALS & INTERFACES Vol.9 No.34

<P>There is a general consensus that the carrier mobility in a field-effect transistor (FET) made of semiconducting transition-metal dichalcogenides (s-TMDs) is severely degraded by the trapping/detrapping and Coulomb scattering of carriers by ionic charges in the gate oxides. Using a double-gated (DG) MoTe2 FET, we modulated and enhanced the carrier mobility by adjusting the top- and bottom-gate biases. The relevant mechanism for mobility tuning in this device was explored using static DC and low-frequency (LF) noise characterizations. In the investigations, LF-noise analysis revealed that for a strong back-gate bias the Coulomb scattering of carriers by ionized traps in the gate dielectrics is strongly screened by accumulation charges. This significantly reduces the electrostatic scattering of channel carriers by the interface trap sites, resulting in increased mobility. The reduction of the number of effective trap sites also depends on the gate bias, implying that owing to the gate bias, the carriers are shifted inside the channel. Thus, the number of active trap sites decreases as the carriers are repelled from the interface by the gate bias. The gate-controlled Coulomb-scattering parameter and the trap-site density provide new handles for improving the carrier mobility in TMDs, in a fundamentally different way from dielectric screening observed in previous studies.</P>

Alloyed 2D Metal–Semiconductor Heterojunctions: Origin of Interface States Reduction and Schottky Barrier Lowering

Kim, Yonghun,Kim, Ah Ra,Yang, Jin Ho,Chang, Kyoung Eun,Kwon, Jung-Dae,Choi, Sun Young,Park, Jucheol,Lee, Kang Eun,Kim, Dong-Ho,Choi, Sung Mook,Lee, Kyu Hwan,Lee, Byoung Hun,Hahm, Myung Gwan,Cho, Byung American Chemical Society 2016 NANO LETTERS Vol.16 No.9

<P>The long-term stability and superior device reliability through the use of delicately designed metal contacts with two-dimensional (2D) atomic-scale semiconductors are considered one of the critical issues related to practical 2D-based electronic components. Here, we investigate the origin of the improved contact properties of alloyed 2D metal semiconductor heterojunctions. 2D WSe2-based transistors with mixed transition layers containing van der Waals (M-vdW, NbSe2/WxNb1-xSe2/WSe2) junctions realize atomically sharp, interfaces, exhibiting long hot-carrier. :lifetimes of approximately 75,296 s (78 times longer than that of metal semiconductor, Pd/WSe2 junctions). Such dramatic lifetime enhancement in M-vdW-junctioned devices is attributed to the synergistic effects arising from the significant reduction in the number of defects and the Schottky barrier lowering at the interface. Formation of a controllable mixed-composition alloyed layer on the 2D active channel would be a breakthrough approach to maximize the electrical reliability of 2D nanomaterial-based electronic applications.</P>

Negative Fermi-Level Pinning Effect of Metal/n-GaAs(001) Junction Induced by a Graphene Interlayer

Yoon, Hoon Hahn,Song, Wonho,Jung, Sungchul,Kim, Junhyung,Mo, Kyuhyung,Choi, Gahyun,Jeong, Hu Young,Lee, Jong Hoon,Park, Kibog American Chemical Society 2019 ACS APPLIED MATERIALS & INTERFACES Vol.11 No.50

<P>It is demonstrated that the electric dipole layer due to the overlapping of electron wave functions at the metal/graphene contact results in a negative Fermi-level pinning effect on the region of the GaAs surface with low interface-trap density in the metal/graphene/n-GaAs(001) junction. The graphene interlayer plays the role of a diffusion barrier, preventing the atomic intermixing at the interface and preserving the low interface-trap density region. The negative Fermi-level pinning effect is supported by the decrease of the Schottky barrier with the increase of the metal work function. Our work shows that the graphene interlayer can invert the effective work function of the metal between high and low, making it possible to form both Schottky and Ohmic-like contacts with identical (particularly high work function) metal electrodes on a semiconductor substrate possessing low surface-state density.</P> [FIG OMISSION]</BR>

Si Surface Passivation by Atomic Layer Deposited Al 2 O 3 with In-Situ H 2 O Prepulse Treatment

김호경,최병준 한국전기전자재료학회 2019 Transactions on Electrical and Electronic Material Vol.20 No.4

We explored the electrical properties of Au/Al 2 O 3 /p-Si diodes subjected to in situ atomic layer deposition (ALD) preceded by H 2 O pulsing, and derived capacitance–voltage ( C – V ) curves. Prepulsed samples exhibited lower frequency dispersion in the accumulation region, and negligible frequency dispersion in the inversion region, compared to control samples. The test samples also showed less marked fl atband voltage shifts in terms of C – V hysteresis (about 60% reduction at 1 MHz). Analysis of frequency-dependent parallel conductance revealed that H 2 O prepulsing reduced the interface trap density. The exponential dependence of the time constant of applied voltage deviated from linearity for samples not subjected to H 2 O prepulsing, attributable to non-uniformity of the oxide charges. Border traps evident in the accumulation region at ~ 0.32 eV above the Si valence band with the time constant about 1 μs were passivated by H 2 O prepulsing. These results suggest thatH 2 O prepulsing is a promising surface treatment for Si prior to ALD deposition.

Engineering of AlON interlayer in Al₂O₃/AlON/In_0.53Ga_0.47As gate stacks by thermal atomic layer deposition

Lee, Woo Chul,Cho, Cheol Jin,Park, Suk-In,Jun, Dong-Hwan,Song, Jin Dong,Hwang, Cheol Seong,Kim, Seong Keun ELSEVIER 2018 CURRENT APPLIED PHYSICS Vol.18 No.8

<P>The presence of an AlN interfacial layer in high-k/In0.53Ga0.47As gate stacks improves the interfacial properties and enhances the electrical performance of devices. However, pure AlN is rarely grown by atomic layer deposition (ALD) because of the low reactivity of NH3 toward the common Al-precursor and the predisposition to oxidation of the grown AlN layer. Although a plasma-enhanced ALD technique significantly suppresses the oxygen content in the grown AlN layer, the deterioration of the interface properties by plasma-damage is a critical issue. In this work, an AlON interlayer was engineered by optimizing the NH3 feeding time in thermal ALD to improve the interface quality in Al2O3/AlON/In0.53Ga0.47As capacitors. It was determined that a mere increase in the NH3 feeding time during the ALD of the AlON film resulted in a higher nitrogen incorporation into the AlON interlayer, leading to a reduction in the interface trap density. Furthermore, the out-diffusion of elements from the In0.53Ga0.47As layer was effectively suppressed by increasing the NH3 feeding time. This work demonstrates that simple process optimization can improve the interface quality in high-k/In0.53Ga0.47As gate stacks without the use of any plasma-activated nitrogen source.</P>

Engineering of AlON interlayer in Al2O3/AlON/In0.53Ga0.47As gate stacks by thermal atomic layer deposition

이우철,조철진,박석인,전동환,송진동,황철성,김성근 한국물리학회 2018 Current Applied Physics Vol.18 No.8

The presence of an AlN interfacial layer in high-k/In0.53Ga0.47As gate stacks improves the interfacial properties and enhances the electrical performance of devices. However, pure AlN is rarely grown by atomic layer deposition (ALD) because of the low reactivity of NH3 toward the common Al-precursor and the predisposition to oxidation of the grown AlN layer. Although a plasma-enhanced ALD technique significantly suppresses the oxygen content in the grown AlN layer, the deterioration of the interface properties by plasma-damage is a critical issue. In this work, an AlON interlayer was engineered by optimizing the NH3 feeding time in thermal ALD to improve the interface quality in Al2O3/AlON/In0.53Ga0.47As capacitors. It was determined that a mere increase in the NH3 feeding time during the ALD of the AlON film resulted in a higher nitrogen incorporation into the AlON interlayer, leading to a reduction in the interface trap density. Furthermore, the out-diffusion of elements from the In0.53Ga0.47As layer was effectively suppressed by increasing the NH3 feeding time. This work demonstrates that simple process optimization can improve the interface quality in high-k/In0.53Ga0.47As gate stacks without the use of any plasma-activated nitrogen source.