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Autonomous Burst Access Control Cooperated with Adjacent Nodes in Wireless Multihop Networks
Yosuke Tanigawa,Makoto Mochiki,Hideki Tode,Koso Murakami 한국멀티미디어학회 2009 한국멀티미디어학회 국제학술대회 Vol.2009 No.-
The authors propose the packet transfer scheduling method to perform efficient data transfer in wireless multibop networks. In the proposed method, we set packet transfer rate, mainly according to the success rate of packet transfer at the sender nodes. In this paper, we consider the packet loads at the receiver nodes, and feed the load information back to the upstream nodes. Moreover, we assign channel resources equally to sender nodes that transfer packet to the same receiver node. Through these proposals, we enhance the network capacity keeping the throughput fairness between nodes.
Ootao, Yoshihiro,Tanigawa, Yoshinobu Techno-Press 2005 Structural Engineering and Mechanics, An Int'l Jou Vol.20 No.5
This paper is concerned with the theoretical treatment of transient thermal stresses involving an orthotropic functionally graded thick strip due to nonuniform heat supply in the width direction. The thermal and thermoelastic constants of the strip are assumed to possess orthotropy and vary exponentially in the thickness direction. The transient two-dimensional temperature is analyzed by the methods of Laplace and finite sine transformations. We obtain the exact solution for the simply supported strip under the state of plane strain. Some numerical results for the temperature change, the displacement and the stress distributions are shown in figures. Furthermore, the influence of the orthotropy and nonhomogeneity of the material is investigated.
Antimetabolite Prodrug Delivery for Non-small Cell Lung Cancer
이루다,Sho Tanigawa,박용일,김훈 한국생물공학회 2023 KSBB Journal Vol.38 No.4
Mitochondria play an essential role in cancer initiation and progression. Research in the past decades suggested a close relation between mitochondrial dysfunction and cancer, including non-small cell lung cancer (NSCLC). In addition, mitochondrial dysfunction causes excess levels of reactive oxygen species (ROS) generation and induces mitophagy for removing damaged mitochondrial. Therefore, the induction of mitophagy against abnormal mitochondria in cancer cells is expected to be a therapeutic strategy for cancer. In this study, we aimed to develop a mitochondria-targeted delivery system for inducing mitophagy-mediated apoptosis in non-small cell lung cancer (NSCLC). We successfully synthesized amphiphilic glycol chitosan conjugated with a disulfide linker (aGCSS) and modified paclitaxel with triphenylphosphonium (PTX-TPP prodrug). These components were used to fabricate redox-sensitive nanoparticles loaded with PTX-TPP (aGC-SS-proPTX NPs). The aGC-SS-proPTX NPs exhibited controlled drug release triggered by high glutathione (GSH) levels and showed enhanced accumulation within the mitochondria due to the triphenylphosphonium modification. In vitro experiments demonstrated that the aGC-SH-proPTX NPs effectively suppressed ATP levels, induced mitophagy, and promoted apoptosis in NSCLC cells. Our findings suggest that the targeted delivery of aGC-SSproPTX NPs triggers mitophagy-mediated apoptosis. This research contributes to the growing understanding of the role of mitochondria in cancer therapy and highlights the potential of targeted mitophagy modulation as a promising approach in NSCLC treatment.
An Interface based on Switched-Capacitor Sample/Hold circuit of Differential Capacitance Transducers
Satomi Ogawa,Takuya Tanigawa,Daisuke Adachi 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
For high-accuracy and high-speed signal processing of differential capacitance transducers, an interface circuitry based on a switched-capacitor sample/hold circuit using unity-gain buffer (UGB) is developed. The interface produces the output voltage which is proportional to the ratio of difference-to-sum of two capacitors of a differential transducer using only single reference voltage, Vr. Hspice simulations are described to predict performances of the interface when implemented by 0.35㎛ n-well CMOS process. Experimental results using discrete components are also given to confirm the principles of operation.
Keisuke Yamamoto,Kazuya Tanigawa,Tetsuo Hironaka,Takashi Ishiguro 대한전자공학회 2015 ITC-CSCC :International Technical Conference on Ci Vol.2015 No.6
A memory based PLD (MPLD) has been proposed as one of reconfigurable device. A MPLD consists of multiple-output look-up tables (MLUTs) which is reconfigurable element diagonally connected by AD pairs. MPLD can improve routing ability among logic elements by increasing the number of AD pairs. However, there is problem that chip area of MLUT will be doubled by each additional AD pairs. On the other hand, if a MLUT with fewer number of AD pairs is used for small chip area, it decreases logic density since many MLUTs are used as a part of routing resources. To solve the problem, we propose a small logic element while keeping routing ability high, compared with MLUT. We adopted selector-based logic element to decrease chip area. From the estimation results in this paper, we found that the number of transistor counts required to implement our proposed logic element is decreased to 18.7 % of transistor counts, compared with MLUT with six AD pairs.
Design Consideration of a Secure Sensor Chip for Home Cancer Examination
Tomohiro Tanaka,Kazuya Tanigawa,Tetsuo Hironaka,Takashi Ishiguro 대한전자공학회 2015 ITC-CSCC :International Technical Conference on Ci Vol.2015 No.6
We propose a secure sensor chip for disposable medical examination for home use. Secure sensor chip is required to have functions for encryption and authentication to prevent personal information leakage. In this paper, we estimated secure sensor chip implementations by specific hardware and micro-controller respectively. As a result, the implementation of specific hardware is 40% of chip area in terms of NAND gates, compared with the micro-controller one.
Development and Evaluation of Raytracing Accelerating Engine with Bit Serial Arithmetic Units
Tomoyuki Kawamoto,Kazuya Tanigawa,Tetsuo Hironaka,Yuhki Yamabe 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
In recent years, development of various rendering algorithm provide photorealistic image. However, requirement of quality for rendering causes significant increase of processing time. Raytracing method can generate high quality images.But, it needs much time to get images. Several methods of parallel computing for high speed processing for raytracing with hardware are discussed. But, the chip of conventional raytracing hardware needs huge area because of parallel arithmetic units on it , which result in difficulty on inserting more processing elements(PEs) into the chip. In this paper, we present hardware design of a raytracing accelerator engine with bit serial arithmetic unit to improve performance. Area of bit serial arithmetic unit is small, and operation performance per the unit area is high. We adopt a dot mode for parallel processing because it can make maximum use of the characteristic of bit serial(BS) arithmetic unit. As the first stage, we design prototype hardware which calculate only the process of highest load ratio in PE, and evaluate it. As a result, prototype hardware is about 5.09 times faster on processing time.