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TLB 및 캐쉬 미스패널티를 개선한 MMU/CC의 VLSI 설계
이광엽 서경대학교 1955 論文集 Vol.23 No.2
This thesis describes a MMU/CC(Memory Management Unit and Cache Controller) promoting the performance of a RISC(Reduced Instruction Set Computer) workstation system. To accomplish the translation of the virtual addresses into the physical addresses, the MMU contains an on-chip,64-entry,fully associative TLB(Translation Lookaside Buffer). The MMU uses a tree-structured page table in order to reduce the size of a page table in main memory. In case of a TLB miss, the table walk searches through a series of four tables in main memory. A PTP cache in designed to reduce the TLB miss penalty during the table walk. The cache portion of the MMU/CC features 2048 direct-mapped cache tage entries and the cache controller which supports write-through mode and copy-back mode. Write-through mode is simpler in respect to its structure however, it has one disadvantage of each write being echoed to main memory. Its effect is significantly reduced by including write buffers. The performance of a MMU/CC is evaluated on a SPARK RISC system using 8 test programs which consist of integer arithmatic programs and a character searching program. The results of evaluation show 1.84% cache miss ratio and 0.17% TLB miss ratio. Also, it is verified that the MMU/CC increases the IU performance up to 40%. The MMU/CC chip is designed using 0.8um polysilicon gate double metal,twin-but CMOS techonology. It contains about 650,000 transistors and 208 pads on the area of 10.1㎜ × 10.9㎜.
Design of a Memory Management Unit and Cache Controller for RISC
Lee, Moon Key,Lee, Kwang Youb,Lee, Seoung Ho,Jeong, Sang Kyu,Jeong, Dae Suk,Kim, Yoon Hak 대한전자공학회 1992 HICEC:Harbin International Conference on Electroni Vol.1 No.1
This paper describes a memory management unit and a cache controller (MMU/CC)for a shared memory multiprocessor. The MMU/CC can be implemented on a single chip. The MMU/CC includes a 64-entry TLB, which consists of a 32 bit CAM and a 32bit RAM. The CAM part of the TLB is divided into four fields because of 4-level page mapping. The MMU/CC supports two modes of caching:write-through with no write allocate and copy-back with write allocate. One of the on-chip cache tag memories has 2048 lines for the external virtual cache, another has a physical cache tag to detect address aliasing. It also implements a snooping bus protocol. The control part of MMU/CC is implemented by 7 FSMs. Each section of the MMU/CC, which totals 17 separate sections, is modeled using Verilog HDL in order to simulate. The MMU/CC is being implemented in a 0.8um double-layer metal CMOS technology, and it will be tested on the board with the SPRAK IU which was developed at Yonsei University.
이광엽(Kwang Youb Lee),이동엽(Dong Yup Lee) 한국정보처리학회 2000 정보처리학회논문지 Vol.7 No.2
This paper describes an IP design of a low-power microcontroller using an architecture level design methodology instead of a transistor level. To reduce switching capacitance, the register-to-register data transfer is adopted to frequently used register transfer micro-operations. Also, distributed buffers are proposed to reduce a input data rising edge time. To reduce power consumption without any loss of performance, pipeline processing should be used. In this paper, a 4-stage pipelined datapath being able to process CISC instructions is designed. Designed microcontroller lessens power consumption by 20%. To measure a power consumption, the SYNOPSYS EPIC powermill is used.