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Nano-scale PMOSFET에서 Plasma Nitrided Oixde에 대한 소자 특성의 의존성
한인식,지희환,구태규,유욱상,최원호,박성형,이희승,강영석,김대병,이희덕,Han, In-Shik,Ji, Hee-Hwan,Goo, Tae-Gyu,You, Ook-Sang,Choi, Won-Ho,Park, Sung-Hyung,Lee, Heui-Seung,Kang, Young-Seok,Kim, Dae-Byung,Lee, Hi-Deok 한국전기전자재료학회 2007 전기전자재료학회논문지 Vol.20 No.7
In this paper, the reliability (NBTI degradation: ${\Delta}V_{th}$) and device characteristic of nano-scale PMOSFET with plasma nitrided oxide (PNO) is characterized in depth by comparing those with thermally nitrided oxide (TNO). PNO case shows the reduction of gate leakage current and interface state density compared to TNO with no change of the $I_{D.sat}\;vs.\;I_{OFF}$ characteristics. Gate oxide capacitance (Cox) of PNO is larger than TNO and it increases as the N concentration increases in PNO. PNO also shows the improvement of NBTI characteristics because the nitrogen peak layer is located near the $Poly/SiO_2$ interface. However, if the nitrogen concentration in PNO oxide increases, threshold voltage degradation $({\Delta}V_{th})$ becomes more degraded by NBT stress due to the enhanced generation of the fixed oxide charges.
Hafnium Oxide를 Trapping Layer로 적용한 Fin-Type SOHOS 플래시 메모리 특성연구
박정규,오재섭,양승동,정광석,김유미,윤호진,한인식,이희덕,이가원,Park, Jeong-Gyu,Oh, Jae-Sub,Yang, Seung-Dong,Jeong, Kwang-Seok,Kim, Yu-Mi,Yun, Ho-Jin,Han, In-Shik,Lee, Hi-Deok,Lee, Ga-Won 한국전기전자재료학회 2010 전기전자재료학회논문지 Vol.23 No.6
In this paper, the electrical characteristics of Fin-type SONOS(silicon-oxide-nitride-oxide-silicon) flash memory device with different trapping layers are analyzed in depth. Two kinds of trapping layers i.e., silicon nitride($Si_3N_4$) and hafnium oxide($HfO_2$) are applied. Compared to the conventional Fin-type SONOS device using the $Si_3N_4$ trapping layer, the Fin-type SOHOS(silicon-oxide-high-k-oxide-silicon) device using the $HfO_2$ trapping layer shows superior program/erase speed. However, the data retention properties in SOHOS device are worse than the SONOS flash memory device. Degraded data retention in the SOHOS device may be attributed to the tunneling leakage current induced by interface trap states, which are supported by the subthreshold slope and low frequency noise characteristics.
Strained-Si PMOSFET에서 디지털 및 아날로그 성능의 캐리어 방향성에 대한 의존성
한인식(In-Shik Han),복정득(Jung-Deuk Bok),권혁민(Hyuk-Min Kwon),박상욱(Sang-Uk Park),정의정(Yi-Jung Jung),신홍식(Hong-Sik Shin),양승동(Seung-Dong Yang),이가원(Ga-Won Lee),이희덕(Hi-Deok Lee) 大韓電子工學會 2010 電子工學會論文誌-SD (Semiconductor and devices) Vol.47 No.8
본 논문에서는 각각 다른 캐리어 방향성을 가지는 strained-silicon PMOSFET에서 소자의 디지털 및 아날로그 성능을 비교 평가 하였다. 캐리어 방향이 〈100〉을 갖는 소자의 경우 이동도 향상에 의해서 〈110〉방향의 소자 보다 우수한 드레인 구동 전류 및 출력저항 특성을 보이지만, NBTI 신뢰성과 소자의 matching 특성은 반대로 다소 열화 됨을 확인 하였다. 따라서 나노미터급 CMOSFET에서 캐리어 방향성을 이용한 이동도 향상 기술의 적용을 위해서는 DC 성능을 비롯한 신뢰성 및 아날로 그 특성을 모두 고려하는 것이 반드시 필요하다고 할 수 있다. In this paper, comparative analysis of digital and analog performances of strained-silicon PMOSFETs with different carrier direction were performed. ID.SAT vs. ID.OFF and output resistance, Rout performances of devices with 〈100〉 carrier direction were better than those of 〈110〉 direction due to the greater carrier mobility of 〈100〉 channel direction. However, on the contrary, NBTI reliability and device matching characteristics of device with 〈100〉 carrier direction were worse than those with 〈110〉 carrier direction. Therefore, simultaneous consideration of analog and reliability characteristics as well as DC device performance is highly necessary when developing mobility enhancement technology using the different carrier direction for nano-scale CMOSFETs.
Nano-CMOSFET를 위한 플라즈마-질화막의 초기 산화막 성장방법에 따른 소자 특성과 저주파 잡음 특성 분석
주한수,한인식,구태규,유옥상,최원호,최명규,이가원,이희덕,Joo, Han-Soo,Han, In-Shik,Goo, Tae-Gyu,Yoo, Ook-Sang,Choi, Won-Ho,Choi, Myoung-Gyu,Lee, Ga-Won,Lee, Hi-Deok 한국전기전자재료학회 2007 전기전자재료학회논문지 Vol.20 No.1
In this paper, two kinds of initial oxidation methods i.e., SLTO(Slow Low Temperature Oxidation: $700^{\circ}C$) and RTO(Rapid Thermal Oxidation: $850^{\circ}C$) are applied prior to the plasma nitridation for ultra thin oxide of RPNO (Remote Plasma Nitrided Oxide). It is observed that SLTO has superior characteristics to RTO such as lower SS(Sub-threshold Slope) and improved Ion-Ioff characteristics. Low frequency noise characteristics of SLTO also showed better than RTO both in linear and saturation regime. It is shown that flicker noise is dominated by carrier number fluctuation in the channel region. Therefore, SLTO is promising for nano-scale CMOS technology with ultra thin gate oxide.
Nano scale PMOSFET에서 Channel Stress에 의한 DC 특성 및 Channel Back Scattering의 변화 관찰
나민기(Min-Ki Na),한인식(In-Shik Han),최원호(Won-Ho Choi),유욱상(Ook-Sang You),권혁민(Hyuk-Min Kwon),박성수,지희환(Hee-Hwan Ji),박성형(Sung-Hyung Park),이가원(Ga-Won Lee),이희덕(Hi-Deok Lee) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
In this paper, both current and channel back scattering on under the channel stress were characterized in depth. The tensile and compressive stresses were applied to PMOSFET using with a nitride film used for the contact etch stop layer (CESL). The subthreshold slope of PMOSFET under compressive stress is smaller than that under the tensile stress, which exhibits the lower off current of compressive stress than tensile stress. Although back scattering ratio (rsat) of compressive stress was larger than tensile stress, thermal injection velocity (Vinj) of compressive stress was much larger than tensile case, which results in larger Idsat for compressive stress case. It was confirmed that the drain current of the device with an uniaxial stress has a strong dependency on the subthreshold slope and thermal injection velocity at the source side.
Nano-Scale CMOSFET에서 Contact Etch Stop Layer의 Mechanical Film Stress에 대한 소자특성 분석
나민기(Min-Ki Na),한인식(In-Shik Han),최원호(Won-Ho Choi),권혁민(Hyuk-Min Kwon),지희환(Hee-Hwan Ji),박성형(Sung-Hyung Park),이가원(Ga-Won Lee),이희덕(Hi-Deok Lee) 대한전자공학회 2008 電子工學會論文誌-SD (Semiconductor and devices) Vol.45 No.4
본 논문에서는 Contact Etch Stop Layer (CESL)인 nitride film의 mechanical stress에 의해 인가되는 channel stress가 소자특성에 미치는 영향에 대해 분석하였다. 잘 알려진 바와 같이 NMOS는 tensile stress와 PMOS에서는 compressive stress가 인가되었을 경우 drain current가 증가하였으며 그 원인을 체계적으로 분석하였다. NMOS의 경우 tensile stress가 인가됨으로써 back scattering ratio (rsat)의 감소와 thermal injection velocity (Vinj)의 증가로 인해 mobility가 개선됨을 확인하였다. 또한 rsat 의 감소는 온도에 따른 mobility의 감소율이 작고, 그에 따른 mean free path ( λO)의 감소율이 작기 때문인 것으로 확인되었다. 한편 PMOS의 compressive stress 경우에는 tensile stress에 비해 온도에 따른 mobility의 감소율이 크기 때문에 channel back scattering 현상은 심해지지만 source에서의 Vinj가 큰 폭으로 증가함으로써 mobility가 개선됨을 확인 할 수 있었다. 따라서 CES-Layer에 의해 인가된 channel stress에 따른 소자 특성의 변화는 inversion layer에서의 channel back scattering 현상과 source에서의 thermal injection velocity에 매우 의존함을 알 수 있다. In this paper, the dependence of MOSFET performance on the channel stress is characterized in depth. The tensile and compressive stresses are applied to CMOSFET using a nitride film which is used for the contact etch stop layer (CESL). Drain current of NMOS and PMOS is increased by inducing tensile and compressive stress, respectively, due to the increased mobility as well known. In case of NMOS with tensile stress, both decrease of the back scattering ratio (rsat) and increase of the thermal injection velocity (Vinj) contribute the increase of mobility. It is also shown that the decrease of the rsat is due to the decrease of the mean free path (λ?). On the other hand, the mobility improvement of PMOS with compressive stress is analyzed to be only due to the so increased Vinj because the back scattering ratio is increased by the compressive stress. Therefore it was confirmed that the device performance has a strong dependency on the channel back scattering of the inversion layer and thermal injection velocity at the source side and NMOS and PMOS have different dependency on them.
Low-Frequency Noise 측정을 통한 Bottom-Gated ZnO TFT의 문턱전압 불안정성 연구
정광석,김영수,박정규,양승동,김유미,윤호진,한인식,이희덕,이가원,Jeong, Kwang-Seok,Kim, Young-Su,Park, Jeong-Gyu,Yang, Seung-Dong,Kim, Yu-Mi,Yun, Ho-Jin,Han, In-Shik,Lee, Hi-Deok,Lee, Ga-Won 한국전기전자재료학회 2010 전기전자재료학회논문지 Vol.23 No.7
Low-frequency noise (1/f noise) has been measured in order to analyze the Vth instability of ZnO TFTs having two different active layer thicknesses of 40 nm and 80 nm. Under electrical stress, it was found that the TFTs with the active layer thickness of 80 nm shows smaller threshold voltage shift (${\Delta}V_{th}$) than those with thickness of 40 nm. However the ${\Delta}V_{th}$ is completely relaxed after the removal of DC stress. In order to investigate the cause of this threshold voltage instability, we accomplished the 1/f noise measurement and found that ZnO TFTs exposed the mobility fluctuation properties, in which the noise level increases as the gate bias rises and the normalized drain current noise level($S_{ID}/{I_D}^2$) of the active layer of thickness 80 nm is smaller than that of active layer thickness of thickness 40 nm. This result means that the 80 nm thickness TFTs have a smaller density of traps. This result correlated with the physical characteristics analysis performmed using XRD, which indicated that the grain size increases when the active layer thickness is made thicker. Consequently, the number of preexisting traps in the device increases with decreasing thickness of the active layer and are related closely to the $V_{th}$ instability under electrical stress.
박성수(Sung-Soo Park),최원호(Won-Ho Choi),한인식(In-Shik Han),나민기(Min-Gi Na),이가원(Ga-Won Lee) 대한전자공학회 2008 電子工學會論文誌-SD (Semiconductor and devices) Vol.45 No.7
본 논문에서는 전하 펌프 방법 (Charge Pumping Method, CPM)를 이용하여 서로 다른 질화막 층을 가지는 N-Channel SANOS (Silicon-Al₂O₃-Nitride-Oxide-Silicon) Flash Memory Cell 트랜지스터의 트랩 특성을 규명하였다. SANOS Flash Memory에서 계면 및 질화막 트랩의 중요성은 널리 알려져 있지만, 소자에 직접 적용 가능하면서 정확하고 용이한 트랩 분석 방법은 미흡하다고 할 수 있다. 기존에 알려진 분석 방법 중 전하 펌프 방법은 측정 및 분석이 간단하면서 트랜지스터에 직접 적용이 가능하여 MOSFET에 널리 사용되어왔으며 최근에는 MONOS/SONOS 구조에도 적용되고 있지만 아직까지는 Silicon 기판과 tunneling oxide와의 계면에 존재하는 트랩 및 tunneling oxide가 얇은 구조에서의 질화막 벌크 트랩 추출 결과만이 보고되어 있다. 이에 본 연구에서는 Trapping Layer (질화막)가 다른 SONOS 트랜지스터에 전하 펌프 방법을 적용하여 Si 기판/Tunneling Oxide 계면 트랩 및 질화막 트랩을 분리하여 평가하였으며 추출된 결과의 정확성 및 유용성을 확인하고자 트랜지스터의 전기적 특성 및 메모리 특성과의 상관 관계를 분석하고 Simulation을 통해 확인하였다. 분석 결과 계면 트랩의 경우 트랩 밀도가 높고 trap의 capture cross section이 큰 소자의 경우 전자이동도, subthreshold slop, leakage current 등의 트랜지스터의 일반적인 특성 열화가 나타났다. 계면 트랩은 특히 Memory 특성 중 Program/Erase (P/E) speed에 영향을 미치는 것으로 나타났는데 이는 계면결함이 많은 소자의 경우 같은 P/E 조건에서 더 많은 전하가 계면결함에 포획됨으로써 trapping layer로의 carrier 이동이 억제되기 때문으로 판단되며 simulation을 통해 서도 동일한 결과를 확인하였다. 하지만 data retention의 경우 계면 트랩보다 charge trapping layer인 질화막 트랩 특성에 의해 더 크게 영향을 받는 것으로 나타났다. 이는 P/E cycling 횟수에 따른 data retention 특성 열화 측정 결과에서도 일관되게 확인할 수 있었다. In this paper, the dependence of electrical characteristics of Silicon-Al₂O₃-Nitride-Oxide -Silicon (SANOS) memory cell transistors and program/erase (P/E) speed, reliability of memory device on interface trap between Si substrate and tunneling oxide and bulk trap in nitride layer were investigated using charge pumping method which has advantage of simple and versatile technique. We analyzed different SANOS memory devices that were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SANOS cell transistors with larger capture cross section and interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. The data retention was deteriorated as increasing P/E cycling number but not coincides with interface trap increasing tendency. This result once again confirmed that interface trap independence on data retention. And the result on different program method shows that HCI program method more degraded by locally trapping. So, we know as a result of experimentthat analysis the SANOS Flash memory characteristic using charge pumping method reflect the device performance related to interface and bulk trap.
Lanthanum이 혼입된 고유전 게이트 산화막에서의 온도에 따른 캐리어 이동 특성
권혁민(Hyuk-Min Kwon),최원호(Won-Ho Choi),한인식(In-Shik Han),구태규(Tae-Gyu Goo),나민기(Min-Ki Na),유욱상(Ook-Sang Yoo),이가원(Ga-Won Lee),이희덕(Hi-Deok Lee) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
In this paper, we analyzed the mechanisms of gate leakage current for high performance MOSFETs with La-incorporated hafnium oxide. Barrier height and trap energy level are extracted using different temperature. The barrier height (1.115eV) of Schottky emission was similar to previously reported value and the trap energy level (1.133eV) of Frenkel-Poole emission was slightly low than reported value, which may be due to the La-incorporation.
나노급 CMOSFET을 위한 니켈-코발트 합금을 이용한 니켈-실리사이드의 열안정성 개선
박기영,정순연,한인식,장잉잉,종준,이세광,이가원,왕진석,이희덕,Park, Kee-Young,Jung, Soon-Yen,Han, In-Shik,Zhang, Ying-Ying,Zhong, Zhun,Li, Shi-Guang,Lee, Ga-Won,Wang, Jin-Suk,Lee, Hi-Deok 한국전기전자재료학회 2008 전기전자재료학회논문지 Vol.21 No.1
In this paper, the Ni-Co alloy was used for thermal stability estimation comparison with Ni structure. The proposed Ni/Ni-Co structure exhibited wider range of rapid thermal process windows, lower sheet resistance in spite of high temperature annealing up to $700^{\circ}C$ for 30 min, more uniform interface via FE-SEM analysis, NiSi phase peak. Therefore, The proposed Ni/Ni-Co structure is highly promising for highly thermal immune Ni-silicide for nano-scale MOSFET technology.