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Post-Metallization Annealing 시 passivation 막이 나노 NMOSFET 용 I/O 소자의 핫-캐리어 특성에 미치는 영향
유욱상(Ooksang Yoo),한인식(Inshik Han),주한수(Hansoo Joo),손영환(Younghwan Son),구태규(Taegyu goo),최원호(Wonho Choi),최성욱(Seongwook Choi),임민규(Mingyu Lim),강영석(Youngseok Kang),이정환(Junghwan Lee),왕진석(Jinsuk Wang),이가원(Gawon 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
In this paper, we analyze effect of passivation(Si₃N₄ film) condition under Post-Metallization Annealing on hot carrier degradation. Very thick Si₃N₄(≥ 10000A) prevents H₂ from diffusing into interface(Si-SiO₂), so that hot carrier degradation gets severe. Therefore PMA is performed before Si₃N₄ deposition for hot carrier immunity.
Nano-scale PMOSFET에서 Plasma Nitrided Oixde에 대한 소자 특성의 의존성
한인식,지희환,구태규,유욱상,최원호,박성형,이희승,강영석,김대병,이희덕,Han, In-Shik,Ji, Hee-Hwan,Goo, Tae-Gyu,You, Ook-Sang,Choi, Won-Ho,Park, Sung-Hyung,Lee, Heui-Seung,Kang, Young-Seok,Kim, Dae-Byung,Lee, Hi-Deok 한국전기전자재료학회 2007 전기전자재료학회논문지 Vol.20 No.7
In this paper, the reliability (NBTI degradation: ${\Delta}V_{th}$) and device characteristic of nano-scale PMOSFET with plasma nitrided oxide (PNO) is characterized in depth by comparing those with thermally nitrided oxide (TNO). PNO case shows the reduction of gate leakage current and interface state density compared to TNO with no change of the $I_{D.sat}\;vs.\;I_{OFF}$ characteristics. Gate oxide capacitance (Cox) of PNO is larger than TNO and it increases as the N concentration increases in PNO. PNO also shows the improvement of NBTI characteristics because the nitrogen peak layer is located near the $Poly/SiO_2$ interface. However, if the nitrogen concentration in PNO oxide increases, threshold voltage degradation $({\Delta}V_{th})$ becomes more degraded by NBT stress due to the enhanced generation of the fixed oxide charges.
Hot carrier 개선을 위한 N2 이온주입에 따른 MOSFET의 Digital/Analog 특성 분석
구태규(Taegyu Goo),한인식(Inshik Han),유욱상(Ooksang Yoo),주한수(Hansoo Joo),최원호(Wonho Choi),손영환(Younghwan Son),이정환(Jeonghwan Lee),강영석(Younseok Kang),임민규(Mingyu Lim),최성욱(Seongwook Chio),이가원(Gawon Lee),왕진석(Jinseok 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
In this paper, we investigated the performance and reliability of the device as formatting LDD(Lightly Doped Drain) with additional N₂ implant process. In case of the N₂ implantation, the TED(Transient Enhanced Diffusion) of boron is suppressed in channel regime and the drain current increased. But hot carrier lifetime is improved. Also, we investigated a change of the effective channel length using CP(Charge Pumping) current method and the analog performance is compared to evaluate DC gain and Rout according N₂ implantation. However, the N₂ implantation did not affect at analog performance. But the drain current at the normalized threshold voltage is degraded in digital performance. Therefore, we proved that the reliability can be improved without degrading Rout performance. The important Input/Output(IO) device in the analog performance is partially adapted for nano CMOS technology.
Nano scale PMOSFET에서 Channel Stress에 의한 DC 특성 및 Channel Back Scattering의 변화 관찰
나민기(Min-Ki Na),한인식(In-Shik Han),최원호(Won-Ho Choi),유욱상(Ook-Sang You),권혁민(Hyuk-Min Kwon),박성수,지희환(Hee-Hwan Ji),박성형(Sung-Hyung Park),이가원(Ga-Won Lee),이희덕(Hi-Deok Lee) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
In this paper, both current and channel back scattering on under the channel stress were characterized in depth. The tensile and compressive stresses were applied to PMOSFET using with a nitride film used for the contact etch stop layer (CESL). The subthreshold slope of PMOSFET under compressive stress is smaller than that under the tensile stress, which exhibits the lower off current of compressive stress than tensile stress. Although back scattering ratio (rsat) of compressive stress was larger than tensile stress, thermal injection velocity (Vinj) of compressive stress was much larger than tensile case, which results in larger Idsat for compressive stress case. It was confirmed that the drain current of the device with an uniaxial stress has a strong dependency on the subthreshold slope and thermal injection velocity at the source side.
Lanthanum이 혼입된 고유전 게이트 산화막에서의 온도에 따른 캐리어 이동 특성
권혁민(Hyuk-Min Kwon),최원호(Won-Ho Choi),한인식(In-Shik Han),구태규(Tae-Gyu Goo),나민기(Min-Ki Na),유욱상(Ook-Sang Yoo),이가원(Ga-Won Lee),이희덕(Hi-Deok Lee) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
In this paper, we analyzed the mechanisms of gate leakage current for high performance MOSFETs with La-incorporated hafnium oxide. Barrier height and trap energy level are extracted using different temperature. The barrier height (1.115eV) of Schottky emission was similar to previously reported value and the trap energy level (1.133eV) of Frenkel-Poole emission was slightly low than reported value, which may be due to the La-incorporation.