http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
TCAD 시뮬레이션을 이용한 Fin형 SONOS Flash Memory의 모서리 효과에 관한 연구
양승동,오재섭,윤호진,정광석,김유미,이상율,이희덕,이가원,Yang, Seung-Dong,Oh, Jae-Sub,Yun, Ho-Jin,Jeong, Kwang-Seok,Kim, Yu-Mi,Lee, Sang-Youl,Lee, Hee-Deok,Lee, Ga-Won 한국전기전자재료학회 2012 전기전자재료학회논문지 Vol.25 No.2
Fin-type SONOS (silicon-oxide-nitride-oxide-silicon) flash memory has emerged as novel devices having superior controls over short channel effects(SCE) than the conventional SONOS flash memory devices. However despite these advantages, these also exhibit undesirable characteristics such as corner effect. Usually, the corner effect deteriorates the performance by increasing the leakage current. In this paper, the corner effect of fin-type SONOS flash memory devices is investigate by 3D Process and device simulation and their electrical characteristics are compared to conventional SONOS devices. The corner effect has been observed in fin-type SONOS device. The reason why the memory characteristic in fin-type SONOS flash memory device is not improved, might be due to existing undesirable effect such as corner effect as well as the mutual interference of electric field in the fin-type structure as reported previously.
SONOS 플래시 메모리 소자의 구조와 크기에 따른 특성연구
양승동,오재섭,박정규,정광석,김유미,윤호진,최득성,이희덕,이가원,Yang, Seung-Dong,Oh, Jae-Sub,Park, Jeong-Gyu,Jeong, Kwang-Seok,Kim, Yu-Mi,Yun, Ho-Jin,Choi, Deuk-Sung,Lee, Hee-Deok,Lee, Ga-Won 한국전기전자재료학회 2010 전기전자재료학회논문지 Vol.23 No.9
In this paper, Fin-type silicon-oxide-nitride-oxide-silicon (SONOS) flash memory are fabricated and the electrical characteristics are analyzed. Compared to the planar-type SONOS devices, Fin-type SONOS devices show good short channel effect (SCE) immunity due to the enhanced gate controllability. In memory characteristics such as program/erase speed, endurance and data retention, Fin-type SONOS flash memory are also superior to those of conventional planar-type. In addition, Fin-type SONOS device shows improved SCE immunity in accordance with the decrease of Fin width. This is known to be due to the fully depleted mode operation as the Fin width decreases. In Fin-type, however, the memory characteristic improvement is not shown in narrower Fin width. This is thought to be caused by the Fin structure where the electric field of Fin top can interference with the Fin side electric field and be lowered.
양승동(Seung-Dong Yang),윤호진(Ho-Jin Yun),김유미(Yu-mi Kim),김진섭(Jin-Seob Kim),엄기윤(Ki-Yun Eom),채성원(Seong-Won Chea),이희덕(Hi-Deok Lee),이가원(Ga-Won Lee) 대한전자공학회 2015 전자공학회논문지 Vol.52 No.8
본 연구에서는 MONOS 플래시 메모리의 blocking oxide/trapping nitride, trapping nitride/tunneling oxide 계면 트랩을 구하기 위해 C-V 방법을 도입하였고, stoichiometric 조건을 만족하는 nitride와 silicon rich nitride를 trapping layer로 갖는 MONOS capacitor를 제작하여 각각의 interface trap 특성을 비교분석하였다. 보고에 따르면 silicon rich nitride 는 stoichiometric nitride에 비해 다수의 shallow trap 이 존재한다고 보고되고 있는데, 본 연구를 통해 이의 정량화가 가능함을 보였다. This paper discusses the capacitance-voltage method in Metal-Oxide-Nitride-Oxide-Silicon (MONOS) devices to analyzed the characteristics of the top oxide/nitride, nitride/bottom oxide interface trap distribution. In the CV method, nitride trap density can be calculated based on the program characteristics of the nitride thickness variations. By applying this method, silicon rich nitride device found to have a larger trap density than stoichiometric nitride device. This result is consistent with previous studies. If this comparison analysis can be expected to result in improved reliability of the SONOS flash memory.
Hafnium Oxide를 Trapping Layer로 적용한 Fin-Type SOHOS 플래시 메모리 특성연구
박정규,오재섭,양승동,정광석,김유미,윤호진,한인식,이희덕,이가원,Park, Jeong-Gyu,Oh, Jae-Sub,Yang, Seung-Dong,Jeong, Kwang-Seok,Kim, Yu-Mi,Yun, Ho-Jin,Han, In-Shik,Lee, Hi-Deok,Lee, Ga-Won 한국전기전자재료학회 2010 전기전자재료학회논문지 Vol.23 No.6
In this paper, the electrical characteristics of Fin-type SONOS(silicon-oxide-nitride-oxide-silicon) flash memory device with different trapping layers are analyzed in depth. Two kinds of trapping layers i.e., silicon nitride($Si_3N_4$) and hafnium oxide($HfO_2$) are applied. Compared to the conventional Fin-type SONOS device using the $Si_3N_4$ trapping layer, the Fin-type SOHOS(silicon-oxide-high-k-oxide-silicon) device using the $HfO_2$ trapping layer shows superior program/erase speed. However, the data retention properties in SOHOS device are worse than the SONOS flash memory device. Degraded data retention in the SOHOS device may be attributed to the tunneling leakage current induced by interface trap states, which are supported by the subthreshold slope and low frequency noise characteristics.
산화막과 질화막 위에 제작된 3D SONOS 다층 구조 플래시 메모리소자의 1/f 잡음 특성 분석
이상율,오재섭,양승동,정광석,윤호진,김유미,이희덕,이가원,Lee, Sang-Youl,Oh, Jae-Sub,Yang, Seung-Dong,Jeong, Kwang-Seok,Yun, Ho-Jin,Kim, Yu-Mi,Lee, Hi-Deok,Lee, Ga-Won 한국전기전자재료학회 2012 전기전자재료학회논문지 Vol.25 No.2
In this paper, we compared and analyzed 3D silicon-oxide-nitride-oxide-silicon (SONOS) multi layer flash memory devices fabricated on nitride or oxide layer, respectively. The device fabricated on nitride layer has inferior electrical properties than that fabricated on oxide layer. However, the device on nitride layer has faster program / erase speed (P/E speed) than that on the oxide layer, although having inferior electrical performance. Afterwards, to find out the reason why the device on nitride has faster P/E speed, 1/f noise analysis of both devices is investigated. From gate bias dependance, both devices follow the mobility fluctuation model which results from the lattice scattering and defects in the channel layer. In addition, the device on nitride with better memory characteristics has higher normalized drain current noise power spectral density ($S_{ID}/I^2_D$>), which means that it has more traps and defects in the channel layer. The apparent hooge's noise parameter (${\alpha}_{app}$) to represent the grain boundary trap density and the height of grain boundary potential barrier is considered. The device on nitride has higher ${\alpha}_{app}$ values, which can be explained due to more grain boundary traps. Therefore, the reason why the devices on nitride and oxide have a different P/E speed can be explained due to the trapping/de-trapping of free carriers into more grain boundary trap sites in channel layer.
수열합성법으로 성장시킨 ZnO 나노 로드기반 TFT 가스 센서 제조 및 특성평가
정준교,윤호진,양승동,박정현,김효진,이가원,Jeong, Jun-Kyo,Yun, Ho-Jin,Yang, Seung-Dong,Park, Jeong-Hyun,Kim, Hyo-Jin,Lee, Ga-Won 한국전기전자재료학회 2017 전기전자재료학회논문지 Vol.30 No.4
In this study, we fabricated a TFT gas sensor with ZnO nanorods grown by hydrothermal synthesis. The suggested devices were compared with the conventional ZnO film-type TFTs in terms of the gas-response properties and the electrical transfer characteristics. The ZnO seed layer is formed by atomic-layer deposition (ALD), and the precursors for the nanorods are zinc nitrate hexahydrate ($Zn(NO_3)_2{\cdot}6H_2O$) and hexamethylenetetramine ($(CH_2)6N_4$). When 15 ppm of NO gas was supplied in a gas chamber at $150^{\circ}C$ to analyze the sensing capability of the suggested devices, the sensitivity (S) was 4.5, showing that the nanorod-type devices respond sensitively to the external environment. These results can be explained by X-ray photoelectron spectroscopy (XPS) analysis, which showed that the oxygen deficiency of ZnO nanorods is higher than that of ZnO film, and confirms that the ZnO nanorod-type TFTs are advantageous for the fabrication of high-performance gas sensors.
Atomic Layer Deposition으로 증착된 Al-doped ZnO Film의 전기적, 구조적 및 광학적 특성 분석
임정수,정광석,신홍식,윤호진,양승동,김유미,이희덕,이가원,Lim, Jung-Soo,Jeong, Kwang-Seok,Shin, Hong-Sik,Yun, Ho-Jin,Yang, Seung-Dong,Kim, Yu-Mi,Lee, Hi-Deok,Lee, Ga-Won 한국전기전자재료학회 2011 전기전자재료학회논문지 Vol.24 No.6
Al-doped ZnO film on glass substrate is deposited by ALD in low temperature, using 4-step process (DEZ-$H_2O$-TMA-$H_2O$). To find out the optimal film condition for TCO material, we fabricate Al-doped ZnO films by increasing Al doping concentration at $100^{\circ}C$, so that the Al-doped film of 5 at% shows the lowest resistivity ($1.057{\times}10^{-2}{\Omega}{\cdot}cm$) and the largest grain size (38.047 nm). Afterwards, the electrical and physical characteristics in Al-doped films of 5 at% are also compared in accordance with increasing deposition temperature. All the films show the optical transmittance over 80% and the film deposited at $250^{\circ}C$ demonstrates the superior resistivity ($1.237{\times}10^{-4}{\Omega}{\cdot}cm$).
저온 다결정 실리콘 박막 트랜지스터의 비정상적인 Hump 현상 분석
김유미,정광석,윤호진,양승동,이상율,이희덕,이가원,Kim, Yu-Mi,Jeong, Kwang-Seok,Yun, Ho-Jin,Yang, Seung-Dong,Lee, Sang-Youl,Lee, Hi-Deok,Lee, Ga-Won 한국전기전자재료학회 2011 전기전자재료학회논문지 Vol.24 No.11
In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density ($D_{it}$) and grain boundary trap density ($N_{trap}$) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.
Al Doped ZnO층 적용을 통한 ZnO 박막 트랜지스터의 전기적 특성과 안정성 개선
엄기윤,정광석,윤호진,김유미,양승동,김진섭,이가원,Eom, Ki-Yun,Jeong, Kwang-Seok,Yun, Ho-Jin,Kim, Yu-Mi,Yang, Seung-Dong,Kim, Jin-Seop,Lee, Ga-Won 한국전기전자재료학회 2015 전기전자재료학회논문지 Vol.28 No.5
Recently, ZnO based oxide TFTs used in the flexible and transparent display devices are widely studied. To apply to OLED display switching devices, electrical performance and stability are important issues. In this study, to improve these electrical properties, we fabricated TFTs having Al doped Zinc Oxide (AZO) layer inserted between the gate insulator and ZnO layer. The AZO and ZnO layers are deposited by Atomic layer deposition (ALD) method. I-V transfer characteristics and stability of the suggested devices are investigated under the positive gate bias condition while the channel defects are also analyzed by the photoluminescence spectrum. The TFTs with AZO layer show lower threshold voltage ($V_{th}$) and superior sub-threshold slop. In the case of $V_{th}$ shift after positive gate bias stress, the stability is also better than that of ZnO channel TFTs. This improvement is thought to be caused by the reduced defect density in AZO/ZnO stack devices, which can be confirmed by the photoluminescence spectrum analysis results where the defect related deep level emission of AZO is lower than that of ZnO layer.