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The Short Channel Effect Immunity of Silicon Nanowire SONOS Flash Memory Using TCAD Simulation
양승동,오재섭,윤효진,정광석,김유미,이상열,이희덕,이가원 한국전기전자재료학회 2013 Transactions on Electrical and Electronic Material Vol.14 No.3
Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage (VT) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.
Analysis of SOHOS Flash Memory with 3-level Charge Pumping Method
양승동,김성현,윤호진,정광석,김유미,김진섭,고영욱,안진운,이희덕,이가원 대한전자공학회 2014 Journal of semiconductor technology and science Vol.14 No.1
This paper discusses the 3-level charge pumping (CP) method in planar-type Silicon-Oxide-High-k-Oxide-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason of the degradation of data retention properties. In the CP technique, pulses are applied to the gate of the MOSFET which alternately fill the traps with electrons and holes, thereby causing a recombination current Icp to flow in the substrate. The 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.
TCAD 시뮬레이션을 이용한 Fin형 SONOS Flash Memory의 모서리 효과에 관한 연구
양승동,오재섭,윤호진,정광석,김유미,이상율,이희덕,이가원,Yang, Seung-Dong,Oh, Jae-Sub,Yun, Ho-Jin,Jeong, Kwang-Seok,Kim, Yu-Mi,Lee, Sang-Youl,Lee, Hee-Deok,Lee, Ga-Won 한국전기전자재료학회 2012 전기전자재료학회논문지 Vol.25 No.2
Fin-type SONOS (silicon-oxide-nitride-oxide-silicon) flash memory has emerged as novel devices having superior controls over short channel effects(SCE) than the conventional SONOS flash memory devices. However despite these advantages, these also exhibit undesirable characteristics such as corner effect. Usually, the corner effect deteriorates the performance by increasing the leakage current. In this paper, the corner effect of fin-type SONOS flash memory devices is investigate by 3D Process and device simulation and their electrical characteristics are compared to conventional SONOS devices. The corner effect has been observed in fin-type SONOS device. The reason why the memory characteristic in fin-type SONOS flash memory device is not improved, might be due to existing undesirable effect such as corner effect as well as the mutual interference of electric field in the fin-type structure as reported previously.
SONOS 플래시 메모리 소자의 구조와 크기에 따른 특성연구
양승동,오재섭,박정규,정광석,김유미,윤호진,최득성,이희덕,이가원,Yang, Seung-Dong,Oh, Jae-Sub,Park, Jeong-Gyu,Jeong, Kwang-Seok,Kim, Yu-Mi,Yun, Ho-Jin,Choi, Deuk-Sung,Lee, Hee-Deok,Lee, Ga-Won 한국전기전자재료학회 2010 전기전자재료학회논문지 Vol.23 No.9
In this paper, Fin-type silicon-oxide-nitride-oxide-silicon (SONOS) flash memory are fabricated and the electrical characteristics are analyzed. Compared to the planar-type SONOS devices, Fin-type SONOS devices show good short channel effect (SCE) immunity due to the enhanced gate controllability. In memory characteristics such as program/erase speed, endurance and data retention, Fin-type SONOS flash memory are also superior to those of conventional planar-type. In addition, Fin-type SONOS device shows improved SCE immunity in accordance with the decrease of Fin width. This is known to be due to the fully depleted mode operation as the Fin width decreases. In Fin-type, however, the memory characteristic improvement is not shown in narrower Fin width. This is thought to be caused by the Fin structure where the electric field of Fin top can interference with the Fin side electric field and be lowered.
양승동(Seung-Dong Yang),윤호진(Ho-Jin Yun),김유미(Yu-mi Kim),김진섭(Jin-Seob Kim),엄기윤(Ki-Yun Eom),채성원(Seong-Won Chea),이희덕(Hi-Deok Lee),이가원(Ga-Won Lee) 대한전자공학회 2015 전자공학회논문지 Vol.52 No.8
본 연구에서는 MONOS 플래시 메모리의 blocking oxide/trapping nitride, trapping nitride/tunneling oxide 계면 트랩을 구하기 위해 C-V 방법을 도입하였고, stoichiometric 조건을 만족하는 nitride와 silicon rich nitride를 trapping layer로 갖는 MONOS capacitor를 제작하여 각각의 interface trap 특성을 비교분석하였다. 보고에 따르면 silicon rich nitride 는 stoichiometric nitride에 비해 다수의 shallow trap 이 존재한다고 보고되고 있는데, 본 연구를 통해 이의 정량화가 가능함을 보였다. This paper discusses the capacitance-voltage method in Metal-Oxide-Nitride-Oxide-Silicon (MONOS) devices to analyzed the characteristics of the top oxide/nitride, nitride/bottom oxide interface trap distribution. In the CV method, nitride trap density can be calculated based on the program characteristics of the nitride thickness variations. By applying this method, silicon rich nitride device found to have a larger trap density than stoichiometric nitride device. This result is consistent with previous studies. If this comparison analysis can be expected to result in improved reliability of the SONOS flash memory.
Performance Study on a Tri-Gate SONOS Flash Memory with Gate Stack Engineering
박정규,양승동,윤호진,정광석,김유미,이희덕,이가원 한국물리학회 2011 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.58 No.51
In this paper, the electrical characteristics of a tri-gate flash memory device are analyzed in depth for different trapping layers. Compared to the planar-type device, the tri-gate flash memory device shows good short-channel effect immunity and high punch-through margin. We fabricated the tri-gate silicon-oxide-High-K-oxide-silicon (SOHOS) flash memory device with a hafnium oxide (HfO_2) trapping layer and compared with the tri-gate silicon-oxide-nitride-oxide-silicon (SONOS) flash memory device. The fabricated tri-gate SOHOS device showed superior program/erase speed, but exhibited poorer retention characteristics. The inferior data retention in the SOHOS device may be attributed to tunneling leakage current induced by interface trap states. In order to improve the data retention, are fabricated a N_2 implantation BE (band gap-engineered) SOHOS flash memory device. It shows that the data retention characteristic in a N_2 implantation SOHOS memory device is improved due to nitrogen-induced deep traps.
Pillar Type Silicon-Oxide-Nitride-Oxide-Silicon Flash Memory Cells with Modulated Tunneling Oxide
이상열,양승동,윤호진,정광석,김유미,김성현,이희덕,이가원 한국전기전자재료학회 2013 Transactions on Electrical and Electronic Material Vol.14 No.5
In this paper, we fabricated 3D pillar type silicon-oxide-nitride-oxide-silicon (SONOS) devices for high density flash applications. To solve the limitation between erase speed and data retention of the conventional SONOS devices,bandgap-engineered (BE) tunneling oxide of oxide-nitride-oxide configuration is integrated with the 3D structure. In addition, the tunneling oxide is modulated by another method of N2 ion implantation (N2 I/I). The measured data shows that the BE-SONOS device has better electrical characteristics, such as a lower threshold voltage (VT)of 0.13 V, and a higher gm.max of 18.6 μA/V and mobility of 27.02 cm2/Vs than the conventional and N2 I/I SONOS devices. Memory characteristics show that the modulated tunneling oxide devices have fast erase speed. Among the devices, the BE-SONOS device has faster program/erase (P/E) speed, and more stable endurance characteristics,than conventional and N2 I/I devices. From the flicker noise analysis, however, the BE-SONOS device seems to have more interface traps between the tunneling oxide and silicon substrate, which should be considered in designing the process conditions. Finally, 3D structures, such as the pillar type BE-SONOS device, are more suitable for next generation memory devices than other modulated tunneling oxide devices.
김성현,양승동,김진섭,정준교,이희덕,이가원 한국전기전자재료학회 2015 Transactions on Electrical and Electronic Material Vol.16 No.4
This research investigates the impact of charge spreading on the data retention of three-dimensional (3D) siliconoxide- nitride-oxide-silicon (SONOS) flash memory where the charge trapping layer is shared along the cell string. In order to do so, this study conducts an electrical analysis of the planar SONOS test pattern where the silicon nitride charge storage layer is not isolated but extends beyond the gate electrode. Experimental results from the test pattern show larger retention loss in the devices with extended storage layers compared to isolated devices. This retention degradation is thought to be the result of an additional charge spreading through the extended silicon nitride layer along the width of the memory cell, which should be improved for the successful 3-D application of SONOS flash devices.
수열합성법으로 성장시킨 ZnO 나노 로드기반 TFT 가스 센서 제조 및 특성평가
정준교,윤호진,양승동,박정현,김효진,이가원,Jeong, Jun-Kyo,Yun, Ho-Jin,Yang, Seung-Dong,Park, Jeong-Hyun,Kim, Hyo-Jin,Lee, Ga-Won 한국전기전자재료학회 2017 전기전자재료학회논문지 Vol.30 No.4
In this study, we fabricated a TFT gas sensor with ZnO nanorods grown by hydrothermal synthesis. The suggested devices were compared with the conventional ZnO film-type TFTs in terms of the gas-response properties and the electrical transfer characteristics. The ZnO seed layer is formed by atomic-layer deposition (ALD), and the precursors for the nanorods are zinc nitrate hexahydrate ($Zn(NO_3)_2{\cdot}6H_2O$) and hexamethylenetetramine ($(CH_2)6N_4$). When 15 ppm of NO gas was supplied in a gas chamber at $150^{\circ}C$ to analyze the sensing capability of the suggested devices, the sensitivity (S) was 4.5, showing that the nanorod-type devices respond sensitively to the external environment. These results can be explained by X-ray photoelectron spectroscopy (XPS) analysis, which showed that the oxygen deficiency of ZnO nanorods is higher than that of ZnO film, and confirms that the ZnO nanorod-type TFTs are advantageous for the fabrication of high-performance gas sensors.