안테나에 커플링되는 협대역 고출력 전자기파에 대한 저잡음 증폭기의 민감성 분석

황선묵,허창수,Hwang, Sun-Mook,Huh, Chang-Su 한국전기전자학회 2015 전기전자학회논문지 Vol.19 No.3

본 연구는 안테나에 커플링되는 협대역 고출력 전자기파에 대한 저 잡음 증폭기(LNA)의 민감성 특성을 알아보았다. LNA 소자의 오동작/파괴는 MFR/DFR((Malfunction Failure Rate/Destruction Failure Rate)을 이용하여 소자의 민감성을 확인하였다. 그리고 LNA 소자의 내부 칩 상태는 Decapsulation 분석을 이용하여 손상부위를 관찰하였다. 협대역 고출력 전자기파 장치는 2.45 GHz 마그네트론을 사용하였고, LNA의 민간성 레벨은 협대역 고출력 전자기파의 전계강도에 따라 오동작/파괴율을 평가하였다. 그 결과, LNA 소자의 오동작은 셀프리셋(Self Reset)과 파워리셋(Power Reset)의 형태로 나타내었고, 이때 오동작 임계 전계강도는 각각 524 V/m, 1150 V/m로 측정되었다. 그리고 LNA의 소자의 파괴 임계 전계강도는 1530 V/m이다. 협대역 고출력 전자기파에 의한 LNA 소자의 내부 칩 파괴는 본드와이어, 온칩와이어 그리고 컴포넌트 세가지 형태로 관찰되었다. 이 결과로, 협대역 고출력 전자기파에 의한 반도체 전자회로의 내성평가 자료로 활용할 수 있을 것으로 판단된다. This study has examined susceptibility of LNA(Low Noise Amplifier) due to Front-Door Coupling under Narrow-Band high power electromagnetic wave. M/DFR(Malfunction/Destruction Failure Rate) was measured to investigate the diagnostic of IC test. In addition, decapsulation analysis was used to understand the inside of the chip state in LNA devices. The experiments is employed as an open-ended waveguide to study the destruction effects of LNA using a 2.45 GHz Magnetron as a high power electromagnetic wave. The susceptibility level of LNA was assessed by electric field strength, and its failure modes were observed. The malfunction of LNA device has showed as the type of self-reset and power-reset. The electric field strength of malfunction threshold is 524 V/m and 1150 V/m respectively. Also, he electric field of destruction threshold is 1530 V/m. Three types of damaged LNA were observed by decapsulation analysis: component, onchipwire, and bondwire destruction. Based on these results, the susceptibility of the LNA can be applied to a database to help elucidate the effects of microwaves on electronic equipment.

65 ㎚ CMOS 기술을 적용한 20 ㎓ 이하의 1 단 저잡음 증폭기 설계

셴예호(Yehao Shen),이재홍(Jaehong Lee),신형철(Hyungcheol Shin) 대한전자공학회 2009 電子工學會論文誌-SD (Semiconductor and devices) Vol.46 No.6

20 ㎓ 이하의 주파수 범위에서 저잡음 증폭기의 성능지수를 최대화하기 위해 65 ㎚ RF CMOS 기술을 이용하여 제작된 입력 트랜지스터의 바이어스 전압과 폭을 최적화 하였다. 만일 13 ㎓ 보다 동작 주파수가 높을 경우, 보다 높은 이득을 확보하기 위해 2단 증폭기의 적용이 필요하였다. 또한 5 ㎓ 보다 낮을 경우, 제한된 범위 내에서의 전력소모를 제어하기 위해, 입력 트랜지스터의 게이트와 소스사이의 추가적인 커패시터를 삽입하였다. 본 논문은 20 ㎓ 이하에서 동작하는 1단 LNA의 전반적인 성능을 검토하였고, 본 접근법은 다른 CMOS LNA 설계 기술에 적용가능하다. One-stage low noise amplifier (LNA) using 65 ㎚ RF CMOS technology below 20 ㎓ is designed to find the optimal bias voltage and optimal width of input transistor so that the maximum figure of merit (FoM) has been achieved. If the frequency is higher than 13 ㎓, the amplifier needs two-stage to achieve the higher gain. If the frequency is lower than 5 ㎓, one additional capacitor between gate and source should be added to control the power under the limitation. This paper summarizes one-stage LNA overall performances below 20 ㎓ and this approach can also be applied to other CMOS technology of LNA designs.

Design Optimization of a One-Stage Low Noise Amplifier below 20 GHz in 65 nm CMOS Technology

센예호,이재홍,신형철,Shen, Ye-Hao,Lee, Jae-Hong,Shin, Hyung-Cheol The Institute of Electronics and Information Engin 2009 電子工學會論文誌-CI (Computer and Information) Vol.46 No.6

20 GHz 이하의 주파수 범위에서 저잡음 증폭기의 성능지수를 최대화하기 위해 65 nm RF CMOS 기술을 이용하여 제작된 입력 트랜지스터의 바이어스 전압과 폭을 최적화하였다. 만일 13 GHz 보다 동작 주파수가 높을 경우, 보다 높은 이득을 확보하기 위해 2단 증폭기의 적용이 필요하였다. 또한 5 GHz 보다 낮을 경우, 제한된 범위 내에서의 전력소모를 제어하기 위해, 입력 트랜지스터의 게이트와 소스사이의 추가적인 커패시터를 삽입하였다. 본 논문은 20 GHz 이하에서 동작하는 1단 LNA의 전반적인 성능을 검토하였고, 본 접근법은 다른 CMOS LNA 설계 기술에 적용가능하다. One-stage low noise amplifier (LNA) using 65 nm RF CMOS technology below 20 GHz is designed to find the optimal bias voltage and optimal width of input transistor so that the maximum figure of merit (FoM) has been achieved. If the frequency is higher than 13 GHz, the amplifier needs two-stage to achieve the higher gain. If the frequency is lower than 5 GHz, one additional capacitor between gate and source should be added to control the power under the limitation. This paper summarizes one-stage LNA overall performances below 20 GHz and this approach can also be applied to other CMOS technology of LNA designs.

Size efficient low-noise amplifier for 2.4 GHz ISM-band transceiver

Jhon, Hee-Sauk,Jung, Hakchul,Jeon, Jongwook,Koo, MinSuk,Park, Byung-Gook,Lee, Jong Duk,Shin, Hyungcheol Wiley Subscription Services, Inc., A Wiley Company 2009 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS Vol.51 No.10

<P>This letter presents the implementation technique to reduce circuit area in designing 2.4 GHz CMOS low-noise amplifier (LNA) using size efficient inductors. We applied a vertically shunt (M6/M5) and a 3-D helical inductor to input and output matching network to obtain low noise figure and to save silicon area, simultaneously. Because these inductors have smaller area occupation, overall Si area was reduced. Moreover, the feedback capacitor, C<SUB>f</SUB> is used to compensate the gain degradation from the high resistive 3-D helical inductor at the LNA output stage. The proposed LNA has a gain of 12.5 dB, noise figure (NF) of 2.72 dB, and −5 dBm IIP3, whereas dissipating 5.3 mA from 1.5 V supply. Without any degradation in terms of circuit performance, the size of proposed LNA is reduced by 49.5% compared with that using the conventional asymmetric inductors. For low cost, the LNA has been fabricated using a 0.18 μm mixed-signal CMOS process with top metal thickness of 0.84 μm. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2304–2308, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24600</P>

Analysis and Design of Broadband Cascode Preamplifier Using microstrip feedback line

Yang, Doo-Yeong 제주대학교 공과대학 첨단기술연구소 2004 尖端技術硏究所論文集 Vol.15 No.1

A broadband, high gain and high power output low noise amplifier (LNA) is designed and fabricated for a down converter in a wireless local loop application. The LNA consists of 3 stages of amplifiers. The 1^(st) stage is designed to reduce the noise level, and the 2^(nd) stage is designed to have maximum gain. The 3^(rd) stage has characteristics of broadband and high power. The stability and the gain flatness of the LNA have been improved by using a matching circuit and a source feedback microstrip line at the first and second stages of the amplifiers. The gain of the LNA is (41±0.5dB) over the broadband (2.15GHz~2.45GHz). In the operating frequency range of a wireless local loop application (2.3GHz~2.33GHz), the measured power gain and VSWR of the LNA are 41.5±0.05dB and 1.36, and the noise figure of the LNA is lower than 0.85dB.

통신용 증폭기의 ESD 고장분석과 대책

황순미(Soon Mi Hwang),정용백(Young baek Jung),김철희(Chul hee Kim),이관훈(Kwan Hoon Lee) 한국신뢰성학회 2011 신뢰성응용연구 Vol.11 No.3

Low-noise amplifier(LNA) is a component that amplifies the signal while lowering the noise figure of high-frequency signal. LNA holds a very important position in RF system so that it is widely used for telecommunication. Electro static discharge(ESD) is the most common cause of malfunction for low-powered components, such as Large Scale Integration and IC type LNA is weak in ESD. This thesis studies static effect of communication LNA. It analyzes ESD effect, which occurs within LNA circuit, and describes testing standard and methods. In order to find out LNA"s susceptiblity to electro static, two well-recognized communication IC type LNA models were selected to be tested. Then static-induced malfunction was carefully analyzed and it suggests architectural problem and improvement from the LNA"s ESD point of view.

GPS용 RF Front-End 수신단을 위한 L 대역 저잡음 증폭기 개발

이병찬,손정택,임정택,이재은,송재혁,김준형,백민석,박종성,이은규,김철영 한국전자파학회 2024 한국전자파학회논문지 Vol.34 No.2

GPS의 프론트-엔드 수신단에서는 잡음 지수가 매우 중요하며 잡음 지수가 낮고 크기가 작은 저잡음 증폭기를 요구한다. 본 논문에서는 0.18 μm CMOS 공정을 이용한 L 대역 저잡음 증폭기의 설계에 관한 내용이다. 저잡음 특성을 위해입력단 직렬 인덕터를 제거하고 트랜지스터의 유효폭(effective width)을 늘려 임피던스 정합을 이루어 냈으며 작은 칩크기를 위해 높은 인덕턴스를 요구하는 인덕터들을 적층 구조로 제작하였다. 제작된 저잡음 증폭기는 1.4 GHz부터 2.1 GHz에 이르는 대역에서 2.5 dB 이하의 잡음 지수, 10.57 dB 이상의 반사손실, 17.3 dB의 최고 이득, 1.05 mm×0.78 mm의크기를 달성하였다. In the front-end receiver of a GPS, the noise figure is extremely important and requires a low-noise amplifier with a low noise figure and small size. This study aims to investigate the design of an L-band low-noise amplifier using the 0.18-μm CMOS process. For low-noise characteristics, the input series inductor was removed, the effective width of the transistor was increased to achieve impedance matching, and the inductors requiring high inductance had laminated structures with small chip sizes. The low-noise amplifier achieved a noise figure of less than 2.5 dB, a return loss of more than 10.57 dB, a peak gain of 17.3 dB, and a size of 1.05 mm×0.78 mm in frequency from 1.4∼2.1 GHz.

GPS용 RF Front-End 수신단을 위한 L 대역 저잡음 증폭기 개발

이병찬(Byeong-Chan Lee),손정택(Jeong-Taek Son),임정택(Jeong-Taek Lim),이재은(Jae-Eun Lee),송재혁(Jae-Hyeok Song),김준형(Joon-Hyung Kim),백민석(Min-Seok Baek),박종성(Jong-Seong Park),이은규(Eun-Gyu Lee),김철영(Choul-Young Kim) 한국전자파학회 2024 한국전자파학회논문지 Vol.35 No.2

GPS의 프론트-엔드 수신단에서는 잡음 지수가 매우 중요하며 잡음 지수가 낮고 크기가 작은 저잡음 증폭기를 요구한다. 본 논문에서는 0.18 μm CMOS 공정을 이용한 L 대역 저잡음 증폭기의 설계에 관한 내용이다. 저잡음 특성을 위해 입력단 직렬 인덕터를 제거하고 트랜지스터의 유효폭(effective width)을 늘려 임피던스 정합을 이루어 냈으며 작은 칩 크기를 위해 높은 인덕턴스를 요구하는 인덕터들을 적층 구조로 제작하였다. 제작된 저잡음 증폭기는 1.4 GHz부터 2.1 GHz에 이르는 대역에서 2.5 dB 이하의 잡음 지수, 10.57 dB 이상의 반사손실, 17.3 dB의 최고 이득, 1.05 mm×0.78 mm의 크기를 달성하였다. In the front-end receiver of a GPS, the noise figure is extremely important and requires a low-noise amplifier with a low noise figure and small size. This study aims to investigate the design of an L-band low-noise amplifier using the 0.18-μm CMOS process. For low-noise characteristics, the input series inductor was removed, the effective width of the transistor was increased to achieve impedance matching, and the inductors requiring high inductance had laminated structures with small chip sizes. The low-noise amplifier achieved a noise figure of less than 2.5 dB, a return loss of more than 10.57 dB, a peak gain of 17.3 dB, and a size of 1.05 mm×0.78 mm in frequency from 1.4∼2.1 GHz.

Q-Band 광대역 저잡음 증폭기 설계

김준형,임정택,이재은,송재혁,손정택,백민석,이은규,최선규,김철영 한국전자파학회 2023 한국전자파학회논문지 Vol.34 No.3

This study presents a Q-band wideband low-noise amplifier (LNA), which is implemented and verified using a 65-nm bulk CMOS process, for millimeter-wave applications. The proposed low-noise amplifier uses a transformer structure at the input stage to obtain broadband input-matching characteristics. Under 1-V supply voltage, the proto-type LNA achieves a simulated peak gain of 22.74 dB with gain variation of ±0.37 dB in frequency band. The simulated noise figure (NF) was 3.27 dB at 40 GHz while consuming 17 mW. The core occupies an area of 0.13 mm2 .

A low-power 3.1–10.6 GHz ultra-wideband CMOS low-noise amplifier with common-gate input stage

Nam-Jin Oh 한국물리학회 2011 Current Applied Physics Vol.11 No.1

A low-power ultra-wideband (UWB) low-noise amplifier (LNA) is proposed exploiting a current-reused technique operating in the frequency range of 3.1―10.6 GHz. The technique stacks two-stage amplifiers in dc, thereby reusing the dc current and saving the power consumption significantly. With the commongate configuration at the input stage, broad-band input matching is obtained with less than ―5 dB input reflection coefficient in 3―10 GHz frequency range. Fabricated with 0.18-mm RFCMOS technology, the proposed LNA achieves about 10 dB power gain and noise figure (NF) of 4.6―7.8 dB within 3 dB bandwidth of 2.2―9.7 GHz. The LNA core excluding the buffer consumes only 2.9 mW from a 1.8 V supply voltage. The input third order intercept point (IIP3) of the LNA is ―8.5 dBm at 6 GHz.