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Electrical Characteristics of Semi-Insulating Polycrystalline Oxygen-Doped Silicon SIPOS Thin films
Lee, Seaung Suk,Kim, Jong Choul,Choi, Jae Sung,Park, Hun Sub,Chun, Hui Gon,Oh, Kye Hwan. 대한전자공학회 1991 ICVC : International Conference on VLSI and CAD Vol.2 No.1
Electrical characteristics of SIPOS(Semi-Insulating Polycrystalline Oxygen Doped-Silicon) thin films deposited by low-pressure chemical vapor deposition(LPCVD) were investigated with different process conditions such as N₂O/SiH₄ gas ratio and deposition temperature. The deposition rate and refractive index decreased with increasing gas ratio. Activation energy of SIPOS reaction was 24.13 Kcal/mole. The SIPOS thin films typically showed high resistance of 8.6∼11 tera-ohm in the range of 610℃∼650℃ deposition temperature. A stable high value of resistance was obtained at the gas ratio of N₂O/SiH₄= 0.1. The results also showed that there were a little change in resistance with the resistor size. Moreover, the film sustained high resistance of about 1.2 tera-ohm even at 85℃. The apparent activation energy was 0.39 eV.
SANOS 메모라 셀 트랜지스터의 다른 Charge Trapping layer에 따른 전기적 특성 및 신뢰성 분석
이승석(Seaung-Suk Lee),배기현(Gi-Hyun Bae),이희덕(Hi-Deok Lee),이가원(Ga Won Lee),박성수(Sung-Soo Park),주한수(Han-Soo Joo),최원호(Won-Ho Choil),한인식(In-shik Han),엄재철(Jae-Chul Om) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
In this paper, we analyzed the process-dependent electric characteristics of Silicon-Al₂O₃-Nitride-Oxide -Silicon (SANDS) memory cell transistors. The devices were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. The program/erase speed and data retention under two different stress conditions, which are Fowler-Nordheim (FN) and Hot-carrier injection (HCI) stress, are evaluated. Besides, the reliability characteristics of SANDS devices were also analyzed by measuring the data retention and endurance properties according to the temperature.
Integration Process and Reliability for SrBi₂ Ta₂O<SUB>9</SUB>-based Ferroelectric Memories
Beelyong Yang,Seaung-Suk Lee,Young Min Kang,Kunm Hwan Noh,Suk Kyoung Hong,Sang Hyun Oh,Eung Youl Kang,Seok Won Lee,Jin Gu Kim,Chung Won Suh,Jin Yong Seong,Chang-Goo Lee,Nam Soo Kang,Young-Jin Park 대한전자공학회 2001 Journal of semiconductor technology and science Vol.1 No.3
MRAM Technology for High Density Memory Application
Kim, Chang-Shuk,Jang, In-Woo,Lee, Kye-Nam,Lee, Seaung-Suk,Park, Sung-Hyung,Park, Gun-Sook,Ban, Geun-Do,Park, Young-Jin The Institute of Electronics and Information Engin 2002 Journal of semiconductor technology and science Vol.2 No.3
MRAM(magnetic random access memory) is a promising candidate for a universal memory with non-volatile, fast operation speed and low power consumption. The simplest architecture of MRAM cell is a combination of MTJ(magnetic tunnel junction) as a data storage part and MOS transistor as a data selection part. This article will review the general development status of MRAM and discuss the issues. The key issues of MRAM technology as a future memory candidate are resistance control and low current operation for small enough device size. Switching issues are controllable with a choice of appropriate shape and fine patterning process. The control of fabrication is rather important to realize an actual memory device for MRAM technology.
FeRAM Technology for System on a Chip
Kang, Hee-Bok,Jeong, Dong-Yun,Lom, Jae-Hyoung,Oh, Sang-Hyun,Lee, Seaung-Suk,Hong, Suk-Kyoung,Kim, Sung-Sik,Park, Young-Jin,Chung, Jin-Young The Institute of Electronics and Information Engin 2002 Journal of semiconductor technology and science Vol.2 No.2
The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.