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I/Q 오차 보정 회로를 갖는 2.5㎓ Quadrature LC VCO 설계
변상진(Sangjin Byun),심재훈(Jae Hoon Shim) 大韓電子工學會 2011 電子工學會論文誌-SD (Semiconductor and devices) Vol.48 No.2
본 논문에서는 Quadrature LC VCO(Voltage controlled oscillator)의 I/Q 오차를 분석하고, 그 분석된 결과를 이용하여 I/Q 오차 보정 회로를 제안한다. 제안된 I/Q 오차 보정 회로는 높은 주파수 대역폭을 요구하는 위상 오차 검출기를 사용하는 대신에 낮은 주파수 대역폭으로도 동작이 가능한 진폭 오차 검출기를 사용한다. 제안된 I/Q 오차 보정 회로의 검증을 위하여 2.5㎓ Quadrature LC VCO가 0.18㎛ CMOS 공정으로 제작 및 측정되었다. 측정결과 제안된 진폭 오차 검출기를 사용해도 기존의 위상 오차 검출기는 사용하는 경우들과 유사한 I/Q 오차 보정 성능을 얻을 수 있음을 확인하였다. 본 I/Q 오차 보정회로는 1.8V 전원 전압에서 0.4㎃ 전류를 소모하며, 차지하는 칩 면적은 0.04㎟이다. In this paper, an analysis on I/Q mismatch characteristics of a quadrature LC VCO(Voltage controlled oscillator) is presented. Based on this analysis, a new I/Q mismatch compensator is proposed. The proposed I/Q mismatch compensator utilizes an amplitude mismatch detector rather than the conventional phase mismatch detector requiring much more wide frequency bandwidth. To verify the proposed circuit, a 2.5㎓ quadrature LC VCO was designed in a 0.18㎛ CMOS process and tested. Test results show that an amplitude mismatch detector achieves similar I/Q mismatch compensation performance as that of the conventional phase mismatch detector. The I/Q mismatch compensator consumes 0.4㎃ from1.8V supply voltage and occupies 0.04㎟.
Closed-Form Equation of Data Dependent Jitter in First Order Low Pass System
Hindawi Publishing Corporation 2014 The Scientific World Journal Vol.2014 No.-
<P>This paper presents a closed-form equation of data dependent jitter (DDJ) in first order low pass systems. The DDJ relates to the system bandwidth, the bit rate, the input rise/fall time, and the number of maximum consecutive identical bits of the data pattern. To confirm the derived equation, simulations have been done with a first order RC low pass circuit for various system bandwidths, bit rates, input rise/fall times, and data patterns. The simulation results agree well with the calculated DDJ values by the derived equation.</P>
Analysis and Design of CMOS Received Signal Strength Indicator
IEEE 2014 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.61 No.10
<P>This paper presents a CMOS received signal strength indicator (RSSI) based on the successive detection architecture. Theoretical analyses of the RSSI value, error, and dynamic range are developed. The RSSI value relates to the single-stage voltage gain and the saturated output voltage level of each limiting ampifier cell. The RSSI error depends only on the single-stage voltage gain and the RSSI dynamic range is determined by both the single-stage voltage gain and the number of stages of a limiter. To confirm the derived equations of the RSSI error and dynamic range, a prototype RSSI and limiter circuit was fabricated. The measured total voltage gain of the implemented six-stage limiter is 60 dB, the bandwidth is 30 MHz and the input sensitivity is -61 dBV. The measured RSSI error is within ±1 dB over 55 dB of the RSSI dynamic range, which agrees well with the predicted values by the derived equations. The implemented RSSI and limiter circuit in a 0.18 μm CMOS process consumes 2.6 mA from a 1.8 V supply voltage.</P>
DFSS기법을 활용한 Rear Axle Mounting 구조 최적화에 대한 사례 연구
이상진(Sangjin Lee),변형배(Hyungbai Byun),백승(Seung Baek) 한국자동차공학회 2011 한국자동차공학회 부문종합 학술대회 Vol.2011 No.5
Stiffness of axle mounting structure is one of basic factors affecting on ride & handling performance of the vehicle. The easiest way to increase stiffness of the structure is increasing thickness of sheet metal panels or adding reinforcement. But that means an increasement of mass and process in manufacturing. Design for six sigma (DFSS) is a practical technique for robust and optimized design in manufacturing industry. In this study we applied DFSS to optimize thickness of panels of rear axle mounting structure for increasing stiffness and decreasing mass of the structure. The design of experiments(DOE) in DFSS is based on Daguch method and finite elements method (FEM) is applied to obtain stiffness of rear axle mounting. Control factors are thickness of 8 panels of the mounting structure, output responses are stiffness and mass of the structure, and noise factor is not applicable as relation between thickness and stiffness is linear.
차상진(Sangjin Cha),이재호(Jae ho Lee),변호원(Ho Won Byun),이을종(Eul jong Lee),김내현(Nae Hyun Kim) 대한기계학회 2011 대한기계학회 춘추학술대회 Vol.2011 No.5
본 연구에서는 자연순환형 수직증발기 내의 과냉비등 열전달 계수는 검토하였다. 실험을 위해 작은 크기의 모델이 사용되었다. 압력손실계산에 Ueda의 마찰손실 상관식, Saha and Zuber의 건도와 기공율 상관식을 적용하고 열전달 계산에는 Roshenow의 중첩모델을 적용한 결과 모형실험데이터를 잘 예측하였다. In this study, an effort has been made to analyze the subcooled boiling heat transfer in a natural circulation vertical evaporator. To verify the analysis, a small-scale model was made and tested. The friction correlation by Ueda, void fraction and quality correlation by Saha and Zuber along with the superposition heat transfer model by Rohsenow yielded a satisfactory agreement with the model test data.