에너지 효율이 높은 이중웨이선택형 연관사상캐시

이성재 ( Sungjae Lee ),강진구 ( Jinku Kang ),이주호 ( Juho Lee ),윤지용 ( Jiyong Youn ),이인환 ( Inhwan Lee ) 한국정보처리학회 2012 정보처리학회논문지. 컴퓨터 및 통신시스템 Vol.1 No.1

본 논문은 레벨1 캐시에서 가장 우수한 수준의 에너지 효율을 제공하는 웨이룩업캐시와 레벨2 캐시에서 가장 높은 에너지 효율을 제공하는 웨이추적캐시의 장점을 결합하여, 모든 레벨의 캐시에서 가장 높은 수준의 에너지 효율을 제공하는 이중웨이선택캐시를 제안한다. Alpha 21264프로세서의 예를 이용한 시뮬레이션 결과에 따르면, 이중웨이선택캐시는 레벨1 명령어캐시에서 일반적인 연관사상캐시에 비해 27.57%의 에너지를 소비하여, 웨이룩업캐시와 같은 수준의 에너지 효율을 제공한다. 그리고 이중웨이선택캐시는 레벨1 데이터 캐시에서 일반적인 연관사상캐시에 비해 28.42%의 에너지를 소비하며, 이는 웨이룩업캐시에 비해 에너지 소비가 15.54% 감소한 것이다. 또한 이중웨이선택캐시는 레벨2 캐시에서 일반적인 연관사상캐시에 비해 15.41%의 에너지를 소비하며, 이는 웨이추적캐시에 비해 에너지 소비가 16.16% 감소한 것이다. The way-lookup cache and the way-tracking cache are considered to be the most energy-efficient when used for level 1 and level 2 caches, respectively. This paper proposes an energy-efficient set-associative cache using the bi-mode way-selector that combines the way selecting techniques of the way-tracking cache and the way-lookup cache. The simulation results using an Alpha 21264-based system show that the bi-mode way-selecting L1 instruction cache consumes 27.57% of the energy consumed by the conventional set-associative cache and that it is as energy-efficient as the way-lookup cache when used for L1 instruction cache. The bi-mode way-selecting L1 data cache consumes 28.42% of the energy consumed by the conventional set-associative cache, which means that it is more energy-efficient than the way-lookup cache by 15.54% when used for L1 data cache. The bi-mode way-selecting L2 cache consumes 15.41% of the energy consumed by the conventional set-associative cache, which means that it is more energy-efficient than the way-tracking cache by 16.16% when used for unified L2 cache. These results show that the proposed cache can provide the best level of energy-efficiency regardless of the cache level.

OpenRISC 코어의 성능향상을 위한 캐쉬 구조 설계

정홍균(Hongkyun Jung),류광기(Kwangki Ryoo) 대한전자공학회 2009 電子工學會論文誌-SD (Semiconductor and devices) Vol.46 No.1

최근 마이크로프로세서의 성능이 빠르게 향상됨에 따라 주 메모리의 접근 시간이 증가하고 있어 캐쉬의 필요성이 증대되고 있다. 직접사상 캐쉬는 주 메모리의 각각의 블록이 하나의 캐쉬 라인에 사상되는 구조로서 사상되는 규칙이 간단하지만 서로 다른 블록이 하나의 캐쉬 라인에 사상될 경우 블록의 충돌에 의한 접근 실패율이 집합연관 캐쉬에 비해 높아진다. 본 논문에서는 OpenRISC 코어의 직접사상의 단점을 개선하기 위해 사원 집합연관 캐쉬 구조를 제시한다. 제시한 캐쉬는 주 메모리의 네 개의 블록이 하나의 캐쉬 라인에 사상되는 구조로서 직접사상 캐쉬에 비해 접근 실패율이 감소한다. 또한 라인 교체 방식으로 Pseudo-LRU 방식을 채택하여 LRU 정보를 저장하는 비트 수를 감소시켰다. FPGA 에뮬레이션을 이용하여 사원 집합연관 캐쉬를 포함한 OpenRISC 코어를 검증하였고, 테스트 프로그램을 이용하여 성능을 측정한 결과, 사원 집합연관 캐쉬를 포함한 OpenRISC 코어의 성능이 기존의 OpenRISC 코어의 성능에 비해 약 50% 향상되었고, 미스율은 15%이상 감소하였다. As the recent performance of microprocessor is improving quickly, the necessity of cache is growing because of the increase of the access time of main memory. Every block of direct-mapped cache maps to one cache line. Although the mapping rule is simple, if different blocks map to one cache line, the miss ratio will be higher than the set-associative cache due to conflicts. In this paper, for the improvement of the direct-mapped cache of OpenRISC, 4-way set-associative cache is proposed. Four blocks of the main memory of the proposed cache map to one cache line so that the miss ratio is less than the direct-mapped cache. Pseudo-LRU Policy, which is one of the Line Replacement Policies, is used for decreasing the number of bits that store LRU value. The OpenRISC core including the 4-way set-associative cache was verified with FPGA emulation. As the result of performance measurement using test program, the performance of the OpenRISC core including the 4-way set-associative cache is higher than the previous one by 50% and the decrease of miss ratio is more than 15%.

The Design of Cache Architecture in 32-bit RISC for the Performance Improvement

Hongkyun Jung,Kwangki Ryoo 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7

In this paper, two-way set-associative cache architecture is proposed in 32-bit RISC-based SoC for the performance improvement. Two-way set-associative cache has lower miss rate than direct-mapped cache. Direct-mapped cache in previous 32-bit RISC was modified into two-way associative cache. The proposed architecture is verified on HDL simulator and is tested on the program that manages student information. The result shows that the total number of clocks decreased by 5545 in the executed program.

Performance Improvement and Power Consumption Reduction of an Embedded RISC Core

Jung, Hong-Kyun,Jin, Xianzhe,Ryoo, Kwang-Ki The Korea Institute of Information and Commucation 2012 Journal of information and communication convergen Vol.10 No.1

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of an embedded RISC core and a clock-gating algorithm with observability don’t care (ODC) operation to reduce the power consumption of the core. The branch prediction algorithm has a structure using a branch target buffer (BTB) and 4-way set associative cache that has a lower miss rate than a direct-mapped cache. Pseudo-least recently used (LRU) policy is used for reducing the number of LRU bits. The clock-gating algorithm reduces dynamic power consumption. As a result of estimation of the performance and the dynamic power, the performance of the OpenRISC core applied to the proposed architecture is improved about 29% and the dynamic power of the core with the Chartered 0.18 ${\mu}m$ technology library is reduced by 16%.

Design of new XOR-based hash functions for cache memories

Cho, S.J.,Choi, U.S.,Hwang, Y.H.,Kim, H.D. Pergamon Press ; Elsevier Science Ltd 2008 COMPUTERS & MATHEMATICS WITH APPLICATIONS - Vol.55 No.9

A hash function H is a computationally efficient function that maps bitstrings of arbitrary length to bitstrings of fixed length, called hash values. Hash functions have a variety of general computational uses. They are used in processors to augment the bandwidth of an interleaved multibank memory or to enhance the utilization of a prediction table or a cache. In this paper, we design new XOR-based hash functions, which compute each set index bit as XOR of a subset of the bits in the address by using the concepts of rank and null space. These are conflict-free hash functions which are of different types according to whether m is even or odd. To apply the constructed hash functions to the skewed-associative cache, we show that the degree of interbank dispersion between two hash functions is maximal.

n-Way Set Associative Cache 와 Fully Associative Cache 의 성능분석

조용훈(Cho Yong Hoon),김정선(Kim Jung Sun) 한국정보처리학회 1997 정보처리학회논문지 Vol.4 No.3

In this paper, the performance of direct mapping caches, 2-, 4-, 8-, ..., 4096-way set associative caches, and fully associative caches are analyized by trace simulation for verifying their effectiveness. In general, it is well known that as n, the number of main memory lines to be stored into one cache line number in direct mapping cache, increases, the performance of the cache memory should get higher linearly. According to our analysis, however, it is not true on all the cache organizations. It is shown that as n increases, miss ratios get lower only when the small cache(less than 256K) using large line size is used. It is also shown that fully associative mapping achieves high performance only when small size cache using large line size is used.

고성능 저전력 하이브리드 L2 캐시 메모리를 위한 연관사상 집합 관리

정보성,이정훈,Jung, Bo-Sung,Lee, Jung-Hoon 대한임베디드공학회 2018 대한임베디드공학회논문지 Vol.13 No.3

STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

이동성 기반의 엣지 캐싱 및 사용자 연결 알고리즘 연구

이태윤 ( Taeyoon Lee ),이수경 ( Sukyoung Lee ) 한국정보처리학회 2023 정보처리학회논문지. 컴퓨터 및 통신시스템 Vol.12 No.2

최근 스마트 디바이스 및 스트리밍 서비스의 수요 증가에 따른 네트워크 트래픽을 효과적으로 관리하기 위한 방법으로 Mobile Edge Computing(MEC)기술이 주목받고 있다. MEC는 Base Station(BS)과 같은 네트워크 엣지에 캐시를 설치함으로써 사용자에게 보다 가까운 곳에서 서비스를 제공하므로 낮은 지연시간을 제공하고, 네트워크 부하를 감소시킬 수 있다. 또한, 엣지 네트워크에서 사용자는 가장 가까운 BS와 연결되는 것보다 요청된 콘텐츠가 캐싱되어 있는 BS와 연결하는 것이 서비스 지연시간 감소에 유리하다. 따라서 본 논문에서는 캐시 적중률 향상을 위한 이동성 기반 캐싱 및 사용자 연결(user association)알고리즘을 제안한다. 제안 알고리즘은 체류시간과 콘텐츠 요청 유사도를 토대로 사용자 연결을 결정하고 콘텐츠를 캐싱한다. 시뮬레이션을 통해 기존 연구 대비 제안 알고리즘의 향상된 캐시 적중률과 감소된 지연시간을 확인한다. Mobile Edge Computing(MEC) is considered as a promising technology to effectively support the explosively increasing traffic demands. It can provide low-latency services and reduce network traffic by caching contents at the edge of networks such as Base Station(BS). Although users may associate with the nearest BSs, it is more beneficial to associate users to the BS where the requested content is cached to reduce content download latency. Therefore, in this paper, we propose a mobility-aware joint caching and user association algorithm to imporve the cache hit ratio. In particular, the proposed algorithm performs caching and user association based on sojourn time and content preferences. Simulation results show that the proposed scheme improves the performance in terms of cache hit ratio and latency as compared with existing schemes.

소형셀 네트워크 누적 통신지연 감소를 위한 강화학습기반 실시간 이용자 접속 및 캐시 교체 기법

정재욱(Jae-Wook Jung),전상은(Sang-Eun Jeon),홍준표(Jun-Pyo Hong) 한국통신학회 2020 韓國通信學會論文誌 Vol.45 No.6