휴대단말기 저장매체인 플래시 메모리 특성 분석

정보성,이정훈 한국정보통신설비학회 2011 정보통신설비학회논문지 Vol.10 No.4

저전력 NAND 플래시 메모리를 위한 필터 버퍼의 효율성 분석

정보성,이정훈,Jung, Bo-Sung,Lee, Jung-Hoon 대한임베디드공학회 2012 대한임베디드공학회논문지 Vol.7 No.4

Currently, NAND Flash memory has been widely used in consumer storage devices due to its non-volatility, stability, economical feasibility, low power usage, durability, and high density. However, a high capacity of NAND flash memory causes the high power consumption and the low performance. In the convention memory research, a hierarchical filter mechanism can archive an effective performance improvement in terms of the power consumption. In order to attain the best filter structure for NAND flash memory, we selected a direct-mapped filter, a victim filter, a fully associative filter and a 4-way set associative filter for comparison in the performance analysis. According to the results of the simulation, the fully associative filter buffer with a 128byte fetching size can obtain the bet performance compared to another filter structures, and it can reduce the energy*delay product(EDP) by about 93% compared to the conventional NAND Flash memory.

이중 NAND 플래시 구조의 버퍼시스템에서 효율적 버퍼 크기

정보성,이정훈,Jung, Bo-Sung,Lee, Jung-Hoon 대한임베디드공학회 2011 대한임베디드공학회논문지 Vol.6 No.6

As we know the effects of cache memory research, instruction and data caches can be separated for higher performance with Harvard CPUs. In this paper, we shows the efficiency of buffer system in the instruction and data flash storage medium. And we analyzed characteristics of the data and instruction flash and evaluated the performance. Finally, we propose the best buffer structure with an optimal block size and buffer size for the instruction and data flash.

다양한 메모리 셀을 결합한 디스크형 플래쉬 메모리 시스템

정보성,이정훈,Jung, Bo-Sung,Lee, Jung-Hoon 대한임베디드공학회 2009 대한임베디드공학회논문지 Vol.4 No.3

We present a flash memory system with low cost and high performance for solid-state disk. The proposed flash system is constructed as a SLC with hot blocks and a MLC with cold blocks. Either the SLC or the MLC is selectively accessed on the basis of a position bit in a mapping table. Our results show that the system enables the SLC size to be reduced by about 80% relative to a conventional SLC while maintaining similar performance. And also, our system can improve a performance by above 60% comparing with a conventional MLC.

저전력 집합연관 캐시를 위한 효과적인 알고리즘

정보성,이정훈 대한임베디드공학회 2014 대한임베디드공학회논문지 Vol.9 No.1

In this paper, we proposed a partial-way set associative cache memory with an effective memory access time and low energy consumption. In the proposed set-associative cache memory, it is allowed to access only a 2-ways among 4-way at a time. Choosing ways to be accessed is made dynamically via the least significant two bits of the tag. The chosen 2 ways are sequentially accessed by the way selection bits that indicate the most recently referred way. Therefore, each entry in the way has an additional bit, that is, the way selection bit. In addition, instead of the 4-way LRU or FIFO algorithm, we can utilize a simple 2-way replacement policy. Simulation results show that the energy*delay product can be reduced by about 78%, 14%, 39%, and 15% compared with a 4-way set associative cache, a sequential-way cache, a way-tracking cache, and a way cache respectively.

Fast NAND Flash Memory System for Instruction Code Execution

정보성,Cheong-Ghil Kim,이정훈 한국전자통신연구원 2012 ETRI Journal Vol.34 No.5

The objective of this research is to design a high-performance NAND flash memory system containing a buffer system. The proposed instruction buffer in the NAND flash memory consists of two parts, that is, a fully associative temporal buffer for temporal locality and a fully associative spatial buffer for spatial locality. A spatial buffer with a large fetching size turns out to be effective for serial instructions, and a temporal buffer with a small fetching size is devised for branch instructions. Simulation shows that the average memory access time of the proposed system is better than that of other buffer systems with four times more space. The average miss ratio is improved by about 70% compared with that of other buffer systems.

고성능 저전력 하이브리드 L2 캐시 메모리를 위한 연관사상 집합 관리

정보성,이정훈,Jung, Bo-Sung,Lee, Jung-Hoon 대한임베디드공학회 2018 대한임베디드공학회논문지 Vol.13 No.3

STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

DRAM&PCM 하이브리드 메모리 시스템을 위한 능동적 페이지 교체 정책

정보성,이정훈,Jung, Bo-Sung,Lee, Jung-Hoon 대한임베디드공학회 2018 대한임베디드공학회논문지 Vol.13 No.5

Phase Change Memory(PCM) with low power consumption and high integration attracts attention as a next generation nonvolatile memory replacing DRAM. However, there is a problem that PCM has long latency and high energy consumption due to the writing operation. The PCM & DRAM hybrid memory structure is a fruitful structure that can overcome the disadvantages of such PCM. However, the page replacement algorithm is important, because these structures use two memory of different characteristics. The purpose of this document is to effectively manage pages that can be referenced in memory, taking into account the characteristics of DRAM and PCM. In order to manage these pages, this paper proposes an page replacement algorithm based on frequently accessed and recently paged. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the energy-delay product by around 10%, compared with Clock-DWF and CLOCK-HM.

지역성을 이용한 하이브리드 메모리 페이지 교체 정책

정보성,이정훈,Jung, Bo-Sung,Lee, Jung-Hoon 대한임베디드공학회 2017 대한임베디드공학회논문지 Vol.12 No.3

To replace conventional DRAM, many researches have been done on nonvolatile memories. The DRAM&PCM hybrid memory is one of the effective structure because it can utilize an advantage of DRAM and PCM. However, in order to use this characteristics, pages can be replaced frequently between DRAM and PCM. Therefore, PCM still has major problem that has write-limits. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an average access time and write count of PCM by utilizing two locality for an effective page replacement. We proposed a page selection algorithm which is recently requested to write in DRAM and an algorithm witch uses two locality in PCM. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM write count by around 22% and the average access time by 31% given the same PCM size, compared with CLOCK-DWF algorithm.

선박성능해석 시간 단축을 위한 다수의 CFD 스케줄링 최적화

정보성,함승호,김지혜 한국CDE학회 2024 한국CDE학회 논문집 Vol.29 No.4

Recently, performance of the ship propulsion is very important due to energy efficiency and greenhouse gas emissions. Therefore, computational Fluid Dynamics (CFD) is frequently used during the design phase to improve performance. Three CFD analyses have to be performed sequentially to calculate the ship's performance: resistance test, propeller open water test, and self-propulsion test. However, due to the limited number of licenses, it takes much time to fin- ish CFD analysis of several ships simultaneously. In this study, we used a constraint satisfac- tion problem (CSP) to schedule the simulations sequentially and set a cumulative constraint for each simulation to constrain the number of simulations that can be processed simultaneously. The CP-SAT solver was used to minimize the time taken for CFD simulations. The optimized simulation times were then visualized using Gannt charts to easily compare the results of sched- uling simulations in vessel number order with the optimization technique. We could see that the analysis time scheduled by the optimization technique was significantly reduced, which resulted in a significant improvement in work efficiency. We also compared the total analysis time to derive the optimal number of licenses.