Vertically stacked microscale organic nonvolatile memory devices toward three-dimensional high integration

Yoo, D.,Song, Y.,Jang, J.,Hwang, W.T.,Jung, S.H.,Hong, S.,Lee, J.K.,Lee, T. Elsevier Science 2015 Organic electronics Vol.21 No.-

In this study, vertically stacked microscale organic resistive nonvolatile memory devices are demonstrated. The fabricated devices consisted of vertically stacked two layers of 32x32 crossbar-structured organic memory devices (total of 2048 memory cells) with a memory-cell size of 7x7μm<SUP>2</SUP> on a SiO<SUB>2</SUB> substrate. The microscale organic memory devices were made using an orthogonal photolithography technique with a highly fluorinated photoresist and development solvent. The vertically stacked microscale organic memory devices showed reproducibility with good endurance, and stability and long retention times (over 10<SUP>4</SUP>s) for both layers. The realization of vertical stacking of microscale organic memory devices might enable the production of organic memory devices toward the three-dimensional integration of organic electronic devices.

Improvement of Storage Performance by HfO2/Al2O3 Stacks as Charge Trapping Layer for Flash Memory- A Brief Review

Fucheng Wang,산얄 심피,최지원,조재웅,Yifan Hu,Xinyi Fan,Suresh Kumar Dhungel,이준신 한국전기전자재료학회 2023 전기전자재료학회논문지 Vol.36 No.3

As a potential alternative to flash memory, HfO2/Al2O3 stacks appear to be a viable option as charge capture layers in charge trapping memories. The paper undertakes a review of HfO2/Al2O3 stacks as charge trapping layers, with a focus on comparing the number, thickness, and post-deposition heat treatment and γ-ray and white x-ray treatment of such stacks. Compared to a single HfO2 layer, the memory window of the 5-layered stack increased by 152.4% after O2 annealing at ±12 V. The memory window enlarged with the increase in number of layers in the stack and the increase in the Al/Hf content in the stack. Furthermore, our comparison of the treatment of HfO2/Al2O3 stacks with varying annealing temperatures revealed that an increased annealing temperature resulted in a wider storage window. The samples treated with O2 and subjected to various γ radiation intensities displayed superior resistance. and the memory window increased to 12.6 V at ±16 V for 100 kGy radiation intensity compared to the untreated samples. It has also been established that increasing doses of white x-rays induced a greater number of deep defects. The optimization of stacking layers along with post-deposition treatment condition can play significant role in extending the memory window.

Improving Cache Locality in Processing-in-Memory Accelerator for Parallel Graph Processing

Hessa Alshamsi,Tae Hee Han(한태희) 대한전자공학회 2021 전자공학회논문지 Vol.58 No.10

Processing-in-memory (PIM)은 그래프 프로세싱의 방대한 데이터 이동 문제를 해결하기 위해 각광받고 있는 솔루션이다. 이를 위해 프로세서를 메모리에 인접한 위치에 배치하여 연산을 수행한다. 하지만 그래프 알고리즘은 불규칙한 메모리 접근 패턴으로 인해 지역성이 좋지못하다. 또한 그래프의 불규칙한 구조는 모든 캐시 미스에 대해 주 메모리에서 데이터 요청을 발생시키기 때문에 시스템 성능을 제한한다. 본 논문에서는 메시지 큐 관리를 통해 PIM 기반 가속기의 캐시 지역성을 개선하는 솔루션을 제안한다. 가속기는 불규칙한 메모리 접근 패턴을 위해 message-triggered 프리페처를 사용하지만 캐시 미스와 주 메모리 접근은 피할 수 없는 문제이다. 우리는 캐시 활용도를 더욱 향상시키기 위해 대기열에 대한 정렬 알고리즘을 연구하였으며, gem5 시뮬레이터를 기반으로 두 개의 그래프 알고리즘 벤치마크에 두 개의 실제 그래프를 적용한 시스템의 성능을 측정하였다. Tesseract 대비 에너지 소비의 증가 없이 PIM system의 miss coverage가 평균 11% 향상되었다. Processing-in-memory (PIM) is a promising solution to the large data movement challenge in graph processing. The computations are performed on the memory side by placing processing units near memory. However, graph algorithms suffer from poor locality due to the irregular memory access pattern. The irregular structure of graphs limits the performance of the system by requesting data from the main memory for every cache miss. In this paper, we propose a solution for improving the spatial cache locality of a PIM-based accelerator by managing its message queue. Although the accelerator uses a message-triggered prefetcher for irregular memory accesses, cache misses and main memory accesses are not avoided. We have developed a sorting algorithm for the queue to further improve cache utilization and used gem5 simulator for the implementation, with two real-world graphs on two graph algorithm benchmarks. When comparing with Tesseract, the results show an average increase of 11% in cache miss coverage of PIM system without increasing energy consumption.

Nonvolatile Memory Characteristics of Double-Stacked Si Nanocluster Floating Gate Transistor

Eunkyeom Kim,Kyongmin Kim,Daeho Son,Jeongho Kim,Kyungsu Lee,Sunghwan Won,Junghyun Sok,Wan-Shick Hong,Kyoungwan Park 대한전자공학회 2008 Journal of semiconductor technology and science Vol.8 No.1

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

Nonvolatile Memory Characteristics of Double-Stacked Si Nanocluster Floating Gate Transistor

Kim, Eun-Kyeom,Kim, Kyong-Min,Son, Dae-Ho,Kim, Jeong-Ho,Lee, Kyung-Su,Won, Sung-Hwan,Sok, Jung-Hyun,Hong, Wan-Shick,Park, Kyoung-Wan The Institute of Electronics and Information Engin 2008 Journal of semiconductor technology and science Vol.8 No.1

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

A Die-Selection Method Using Search-Space Conditions for Yield Enhancement in 3D Memory

Joohwan Lee,KiHyunPark,강성호 한국전자통신연구원 2011 ETRI Journal Vol.33 No.6

Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical buses across memory layers will likely be the first commercial application of 3D integrated circuit technology. The memory dies to stack together in a 3D memory are selected by a die-selection method. The conventional die-selection methods do not result in a high-enough yields of 3D memories because 3D memories are typically composed of known-good-dies (KGDs), which are repaired using self-contained redundancies. In 3D memory, redundancy sharing between neighboring vertical memory dies using TSVs is an effective strategy for yield enhancement. With the redundancy sharing strategy, a known-bad-die (KBD) possibly becomes a KGD after bonding. In this paper, we propose a novel die-selection method using KBDs as well as KGDs for yield enhancement in 3D memory. The proposed die-selection method uses three search-space conditions, which can reduce the search space for selecting memory dies to manufacture 3D memories. Simulation results show that the proposed die-selection method can significantly improve the yield of 3D memories in various fault distributions.

3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array

KIM, Yoon,CHO, Seongjae,LEE, Gil Sung,PARK, Il Han,LEE, Jong Duk,SHIN, Hyungcheol,PARK, Byung-Gook The Institute of Electronics, Information and Comm 2009 IEICE transactions on electronics Vol.92 No.5

<P>We propose a 3-dimensional terraced NAND flash memory. It has a vertical channel so it is possible to make a long enough channel in 1F<SUP>2</SUP> size. And it has 3-dimensional structure whose channel is connected vertically along with two stairs. So we can obtain high density as in the stacked array structure, without silicon stacking process. We can make NAND flash memory with 3F<SUP>2</SUP> cell size. Using SILVACO ATLAS simulation, we study terraced NAND flash memory characteristics such as program, erase, and read. Also, its fabrication method is proposed.</P>

다중준위 상변환 메모리를 위한 Ge2Sb2Te5/Ti/W-Ge8Sb2Te11 구조의 전기적 특성 연구

오우영,이현용 한국전기전자재료학회 2022 전기전자재료학회논문지 Vol.35 No.1

In this paper, we investigated current (I)- and voltage (V)-sweeping properties in a double-stack structure, Ge2Sb2Te5/Ti/W-doped Ge8Sb2Te11, a candidate medium for applications to multilevel phase-change memory. 200-nm-thick Ge2Sb2Te5 and W-doped Ge8Sb2Te11 films were deposited on p-type Si(100) substrate using magnetron sputtering system, and the sheet resistance was measured using 4 point-probe method. The sheet resistance of amorphous-phase W-doped Ge8Sb2Te11 film was about 1 order larger than that of Ge2Sb2Te5 film. The I- and V-sweeping properties were measured using sourcemeter, pulse generator, and digital multimeter. The speed of amorphous-to-multilevel crystallization was evaluated from a graph of resistance vs. pulse duration (t) at a fixed applied voltage (12 V). All the double-stack cells exhibited a two-step phase change process with the multilevel memory states of high-middle-low resistance (HR-MR-LR). In particular, the stable MR state is required to guarantee the reliability of the multilevel phase-change memory. For the Ge2Sb2Te5 (150 nm)/Ti (20 nm)/WGe8Sb2Te11 (50 nm), the phase transformations of HR→MR and MR→LR were observed at t<30ns and t<65ns, respectively. We believe that a high speed and stable multilevel phase-change memory can be optimized by the double-stack structure of proper Ge-Sb-Te films separated by a barrier metal (Ti).

기계 장비의 장단기 운용을 고려한 Long Short-Term Memory 기법에 의한 하중 인식

강정호(Jung Ho Kang) 한국기계가공학회 2024 한국기계가공학회지 Vol.23 No.2

Artificial Neural Network has been developed to enable the intelligence of mechanical equipment and devices. However, research on the intelligence of mechanical structures is rare. This study examined the possibility of learning structural loads, which is an important factor in the design and analysis of machines, using long short-term memory (LSTM), which is a Recurrent Neural Network. Because the machine structure operates for a long time, the investigation of the possibility of load learning using Long Short-Term Memory with a memory function for the short and long terms can have important implications for recognizing and predicting accidents and damage during the operation period. Depending on the size of the load, the data entered sequentially tended to be related to predictive accuracy, from relatively old low loads that required long-term memory to large loads that required new and short-term memory. Because the amount of data obtained by structural analysis is insufficient for learning Artificial Neural Networks, its usefulness was confirmed by investigating the possibility of utilizing the data that amplified the data calculated as a result of the structural analysis using the stacked autoencoder.

바이너리 수준에서의 Jump-Oriented Programming에 대한 탐지 메커니즘

김주혁,이요람,오수현 한국정보보호학회 2012 정보보호학회논문지 Vol.22 No.5

It is known that memory has been frequently a target threatening the computer system's security while attacks on the system utilizing the memory's weakness are actually increasing. Accordingly, various memory protection mechanisms have been studied on OS while new attack techniques bypassing the protection systems have been developed. Especially, buffer overflow attacks have been developed as attacks of Return to Library or Return-Oriented Programing and recently, a technique bypassing the countermeasure against Return-Oriented Programming proposed. Therefore, this paper is intended to suggest a detection mechanism at binary level by analyzing the procedure and features of Jump-Oriented Programming. In addition, we have implemented the proposed detection mechanism and experimented it may efficiently detect Jump-Oriented Programming attack. 컴퓨터 시스템의 안전성을 위협하는 주요 취약점으로 메모리 관련 취약점이 알려져 있으며, 최근 들어 이러한 메모리 취약점을 이용한 시스템 상에서의 실제 공격 또한 증가하고 있다. 이에 따라 시스템을 보호하기 위해서 다양한 메모리 보호 메커니즘들이 연구되고 운영체제를 통해 구현되어 왔지만, 더불어 이를 우회할 수 있는 공격 기법들 또한발전하고 있다. 특히 버퍼 오버플로우 공격은 Return to Library, Return-Oriented Programming 등의 공격기법으로 발전되어왔으며, 최근에는 Return-Oriented Programming 공격 기법에 대한 보호 방법 등의 연구로인해 이를 우회하는 Jump-Oriented Programming 공격 기법이 등장하였다. 따라서 본 논문에서는 메모리 관련공격 기법 중 최근 등장한 Jump-Oriented Programming 공격 기법에 대해 살펴보고, 이에 대한 특징을 분석한다. 또한, 분석된 특징을 통한 바이너리 수준에서의 탐지 메커니즘을 제안하고, 실험을 통해 제안하는 방법이Jump-Oriented Programming 공격에 대한 탐지가 가능함을 검증한다.