Silicide-Enhanced Rapid Thermal Annealing을 이용한 다결정 Si 박막의 제조 및 다결정 Si 박막 트랜지스터에의 응용

김존수,문선홍,양용호,강승모,안병태,Kim, Jone Soo,Moon, Sun Hong,Yang, Yong Ho,Kang, Sung Mo,Ahn, Byung Tae 한국재료학회 2014 한국재료학회지 Vol.24 No.9

Amorphous (a-Si) films were epitaxially crystallized on a very thin large-grained poly-Si seed layer by a silicide-enhanced rapid thermal annealing (SERTA) process. The poly-Si seed layer contained a small amount of nickel silicide which can enhance crystallization of the upper layer of the a-Si film at lower temperature. A 5-nm thick poly-Si seed layer was then prepared by the crystallization of an a-Si film using the vapor-induced crystallization process in a $NiCl_2$ environment. After removing surface oxide on the seed layer, a 45-nm thick a-Si film was deposited on the poly-Si seed layer by hot-wire chemical vapor deposition at $200^{\circ}C$. The epitaxial crystallization of the top a-Si layer was performed by the rapid thermal annealing (RTA) process at $730^{\circ}C$ for 5 min in Ar as an ambient atmosphere. Considering the needle-like grains as well as the crystallization temperature of the top layer as produced by the SERTA process, it was thought that the top a-Si layer was epitaxially crystallized with the help of $NiSi_2$ precipitates that originated from the poly-Si seed layer. The crystallinity of the SERTA processed poly-Si thin films was better than the other crystallization process, due to the high-temperature RTA process. The Ni concentration in the poly-Si film fabricated by the SERTA process was reduced to $1{\times}10^{18}cm^{-3}$. The maximum field-effect mobility and substrate swing of the p-channel poly-Si thin-film transistors (TFTs) using the poly-Si film prepared by the SERTA process were $85cm^2/V{\cdot}s$ and 1.23 V/decade at $V_{ds}=-3V$, respectively. The off current was little increased under reverse bias from $1.0{\times}10^{-11}$ A. Our results showed that the SERTA process is a promising technology for high quality poly-Si film, which enables the fabrication of high mobility TFTs. In addition, it is expected that poly-Si TFTs with low leakage current can be fabricated with more precise experiments.

Characteristics of Schottky-barrier Source/Drain Metal-oxide-polycrystalline Thin-film Transistors on Glass Substrates

Seung-Min Jung,조원주,정종완 한국물리학회 2012 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.60 No.1

Polycrystalline-silicon (poly-Si) Schottky-barrier thin-film transistors (SB-TFTs) with Ptsilicided source/drain junctions were fabricated on glass substrates, and the electrical characteristics were examined. The amorphous silicon films on glass substrates were converted into high-quality poly-Si by using excimer laser annealing (ELA) and solid phase crystallization (SPC) methods. The crystallinity of poly-Si was analyzed by using scanning electron microscopy, transmission electron microscopy, and X-ray diffraction analysis. The silicidation process was optimized by measuring the electrical characteristics of the Pt-silicided Schottky diodes. The performances of Pt-silicided SB-TFTs using poly-Si films on glass substrates and crystallized by using ELA and SPC were demonstrated. The SB-TFTs using the ELA poly-Si film demonstrated better electrical performances such as higher mobility (22.4 cm2/Vs) and on/off current ratio (3 × 106) and lower subthreshold swing value (120 mV/dec) than the SPC poly-Si films. Polycrystalline-silicon (poly-Si) Schottky-barrier thin-film transistors (SB-TFTs) with Ptsilicided source/drain junctions were fabricated on glass substrates, and the electrical characteristics were examined. The amorphous silicon films on glass substrates were converted into high-quality poly-Si by using excimer laser annealing (ELA) and solid phase crystallization (SPC) methods. The crystallinity of poly-Si was analyzed by using scanning electron microscopy, transmission electron microscopy, and X-ray diffraction analysis. The silicidation process was optimized by measuring the electrical characteristics of the Pt-silicided Schottky diodes. The performances of Pt-silicided SB-TFTs using poly-Si films on glass substrates and crystallized by using ELA and SPC were demonstrated. The SB-TFTs using the ELA poly-Si film demonstrated better electrical performances such as higher mobility (22.4 cm2/Vs) and on/off current ratio (3 × 106) and lower subthreshold swing value (120 mV/dec) than the SPC poly-Si films.

산화 실리콘의 결정화에 의한 다결정 실리콘의 형성

윤종환 한국물리학회 2018 새물리 Vol.68 No.8

알루미늄 촉매를 사용하여 산화실리콘(SiO$_x$)으로부터 다결정 실리콘(poly-Si)을 형성하였다. Poly-Si은 SiO$_x$/Al/glass 적층 구조를 550 $^\circ$C 온도에서 5시간 동안 열처리하여 형성하였으며, 라만 분광, 엑스선 회절 분광 및 전자투과 현미경 사용하여 결정성을 조사하였다. 산소 조성 값($x$ 값)이 다른 poly-Si 형성 사이의 관련성을 조사하였으며, $x$ = 0인 비정질 실리콘(a-Si)에 비해 SiO$_x$ 박막에서 polly-Si의 형성이 쉽게 이루어지는 거동을 관측하였다. Poly-Si 막은 층 교환 메카니즘에 의해 형성되며 (111) 방향의 선호 배향성을 갖는 것으로 확인되었다. Polycrystalline silicon (poly-Si) was fabricated from silicon oxide (SiO$_x$) by using Al as a catalyst. The fabrication of poly-Si was achieved by annealing SiO$_x$/Al/glass stacked structures at 550 $^\circ$C for 5 hours, with the SiO$_x$ films having different oxygen compositions ($x$ value). Raman, X-ray diffraction (XRD) and transmission electron microscope (TEM) measurements were used to investigate the crystallinity. Poly-Si was observed to occur SiO$_x$ more easily than in amorphous silicon, which has an $x$ value of zero. The formation of the poly-Si film was observed to proceed by a layer-exchange mechanism, and the film was found to have a preferential orientation in the (111) direction.

High charge storage of poly-Si thin film nonvolatile memory devices with oxide@?silicon@?oxynitride stack structures

Jung, S.,Jang, K.,Lee, Y.J.,Jin, Z.,Yi, J. Elsevier 2010 Materials science and engineering B. Advanced Func Vol.167 No.3

Polycrystalline silicon (poly-Si) thin film nonvolatile memory (NVM) devices with an oxide-silicon-oxynitride (OSOn) stack structure using an amorphous silicon (a-Si) as a storage layer on a glass panel were fabricated and investigated for high charge storage of memory applications in systems-on-panels (SOPs). Because the band gap of a-Si is lower than that of silicon nitride (SiNx) and a larger band gap offset provides more room for charge storage, a-Si thin layer with high charge injection can be applied to the fabrication of poly-Si NVM devices. The trap densities of a-Si thin films deposited by different flow ratios of H<SUB>2</SUB>and silane (SiH<SUB>4</SUB> were calculated to determine the optimal conditions for the charge storage layer. Poly-Si thin film transistor (TFT) technology, plasma-assisted oxynitridation to deposit an ultra-thin tunneling layer, and an optimal a-Si thin film charge storage layer were used to fabricate poly-Si NVM devices on glass substrate. A large memory window of +3.02V to -1.68V was obtained at a low operating voltage with an erasing voltage of +10V and a programming voltage of -10V due to high charge storage sites in the a-Si thin film. Our results demonstrate that poly-Si NVM devices with a-Si thin film as a charge storage layer on a glass panel can be applied to system applications of flat panel displays (FPDs) due to their large memory windows at low operating voltage.

비정질/다결정규소 적층형 태양전지

김도영,김상수,박용관,이준신 成均館大學校 科學技術硏究所 1997 論文集 Vol.48 No.1

본 연구는 최근의 지상전력 응용을 위한 Metal/a-Si:H(n-i-p)/poly-Si(n-p)/Metal 구조를 가지는 적층형 태양전지를 연구하였다. 이 전지는 두 층의 동종접합이 적층된 전지구조로 구성되었다. 상부는 1.8eV의 큰 에너지 밴드갭을 가지는 n-i-p형 a-Si:H와 하부전지는 1.1eV의 작은 에너지 밴드갭의 다결정 규소 전지의 n-p형 접합이다. 태양전지의 효율 영향요소를 PC-1D 태양전지 모의실험을 통해 조사한후 실제 소자 제작에 적용하였다. 주요 연구 분야는 3가지로 구분되며 첫째는 p-n접합 다결정 규소의 하부 전지, 둘째는 p-i-n접합 수소화 비정질 상부규소, 세 번째로 적층형 전지의 계면층에 대한 영향이다. 하부전지의 효율은 900℃의 전열처리, 표면처리, 0.43㎛의 에미터 두께, 상부 Yb 금속, 7% 정도의 태양전지 그리드 면적으로 향상되었다. 최적화된 전지 공정으로부터 약 16%의 변환효율을 달성하였다. 상부전지는 이온에 의한 박막의 손상이 없고 우수한 p/i-a-Si:H 계면층을 가지는 광-CVD 시스템을 사용하여 성장하였다. 적층형 계면효과는 세가지의 화학적인 표면처리, 열산화에 의한 표면처리, 그리고 Yb 금속의 상태등의 경우를 연구하였다. 열산화막에 의해 표면처리된 전지는 높은 광전류의 생성과 향상된 분광반응도를 보이고 있다. We investigated multi-stacked solar cells with a structure of metal/a-Si:H(n-i-p)/ poly-Si(n-p)/metal for the terrestrial applications. This cell consists of two component cells: a top n-i-p junction a-Si:H cell with wide-bandgap 1.8eV and a bottom n-p junction poly-Si cell with narrow-bandgap 1.1eV. The efficiency influencing factors of the solar cell were investigated in terms of simulations and experiments. Three main topics of the investigated study were the bottom cell with n-p junction poly-Si, the top a-Si:H cell with n-i-p junction, and the interface layer effects of multi-stacked cell. The efficiency of bottom cell was improved with a pretreatment temperature of 900℃, surface polishing, emitter thickness of 0.43μm, top Yb metal, and grid finger shading of 7% coverage. The process optimized cell showed a conversion efficiency about 16%. Top cell was grown by using a photo-C JD system which gave an ion damage free and good p/i-a-Si:H layer interface. The multi-stacked interface effect was examined with three different surface states; a chemical passivation, thermal oxide passivation, and Yb metal. The oxide passivated cell exhibited the higher photocurrent generation and better spectral response.

수소화된 비정질 규소와 다결정 규소 박막의 반송자 이동도

최유신,정세민,안두수,이준신 成均館大學校 科學技術硏究所 1997 論文集 Vol.48 No.1

열처리는 규소 박막의 구조적, 광학적 성질뿐만 아니라 반송자 이동도 특성을 변화시킨다. 반송자 이동도는 주파수 응답 또는 시간 응답을 통해 소자의 동작에 영향을 끼친다. 본 논문은 수소화된 비정질 실리콘(a-Si:H)의 이동도 변화를 열처리 온도의 함수로써 살펴보았다. 이동도 측정에서 사용된 방법들에 대한 장단점들에 대해 검토하였다. 홀 효과와 Haynes-Shockley 방법은 a-Si:H 박막의 이동도 결정에 대한 오류를 나타내었다. TOF법은 a-Si:H에는 적용 가능하지만 높은 암전류때문에 다결정 실리콘(poly -Si)에는 적용할 수가 없다. 전도를 제한하는 공간전하, 박막 트랜지스터, 과도 전류 관찰방법등은 a-Si:H와 poly-Si의 이동도를 결정할 수 있었다. 규소 박막의 전계효과 이동도는 700℃이상의 고온처리와 RF 플라즈마 재수소화후에 20∼67㎠로 상승된 값을 얻었다. 우리는 박막 트랜지스터(TFT)와 과도 전류 관찰방법은 박막 실리콘 분석에 적당하다는 결론을 얻었다. The carrier mobility influences the device behavior through its frequency response or time response. This paper summarizes the mobility changes of the a-Si:H as a function of anneal temperature. The anneal treatment changes the carrier mobilities of thin film Si as well as optical and structural properties. The advantages and disadvantages were discussed for the employed methods in mobility measurement. Hall effect and Haynes-Shockley (HS) method exhibited some errors for a-Si:H mobility determination. A time of flight (TOF) method was attractive for the a-Si:H but not applicable for the poly-Si films because of high dark current. Space charge limited conduction (SCLC), thin film transistor (TFT), and transient current observation methods were able to determine the mobilities of a-Si:H and poly-Si films. A very high field effect mobility of 20-67㎠/V.s was observed after the high temperature anneal above 700℃, and grain boundary passivation using a RF plasma rehydrogenation. We learned that thin film transistor and transient current observation methods are suitable for the analysis of thin film Si.

Al-Si 층교환 성장에서 ZnO 표면 거칠기가 Si 결정성에 미치는 영향

장원범,최성국,정수훈,이정우,장지호,Kosuke HARA,Haruna WATANABE,Noritaka USAMI 한국물리학회 2013 새물리 Vol.63 No.11

We have investigated the effect of the surface roughness of the zinc-oxide (ZnO) layer on the growth of a by using the polycrystalline-Si (poly-Si) layer Al-induced layer-exchange process. We found that the growth rate, grain size, crystallized fraction and preferential orientation were closely related to the surface roughness of the underlying ZnO layer. As the ZnO surface became rougher, the growth rate, grain size, and crystallized fraction increased, and a preferential orientation in the (100) direction appeared as well. The poly-Si layer that formed on ZnO with a root-mean-square roughness of 2.4 nm revealed a fast growth time (40 minutes), a large grain size (20 μm) and a high crystallized fraction (51%) with a preferential (100) orientation. 고효율 박막 태양전지의 구현을 위해 ZnO (Zinc Oxide) 박막위에 Al-Si 층교환 성장방법 (layer exchange method)을 이용하여 다결정 실리콘 (poly-Si)을 성장하였다. 특히 본 연구에서는 ZnO의 표면 거칠기가 다결정 Si 결정성에 미치는 영향을 조사하였다. ZnO 표면 거칠기에 따른 다결정 Si의 결정립의 크기 (grain size), 정렬방향 변화를 성장 중 현미경 관찰, Field-emission scanning electron microscope (FE-SEM)측정과 Electron backscatter diffraction (EBSD)을 이용해 조사하였다. ZnO의 표면 거칠기가 증가 할 수록 결정화 속도와 결정립 크기가 증가하였으며, (100)배향이 관찰되었다. 결과적으로 표면 거칠기가 2.4 nm 인 ZnO 를 이용하여 20 μm 이상의 입자크기와 높은 결정화도를 가지며 51% 이상의 (100) 배향성을 갖는 다결정 Si 박막이 구현되어, 높은 효율을 갖는 다결정 Si 박막 태양전지의 성능 향상에 기여할 수 있는 가능성을 제시하였다.

System-on-Glass를 구현하기 위한 저항 matching 및 poly-Si TFT특성을 기존 아날로그 회로를 이용하여 분석

김대준,이균렬,유창식,Kim Dae-June,Lee Kyun-Lyeol,Yoo Changsik 대한전자공학회 2005 電子工學會論文誌-SD (Semiconductor and devices) Vol.42 No.2

System-on-Glass 아날로그 회로를 구현하기 위해 요구되는 저항 matching 및 poly-Si TFT 특성을 기존 아날로그 회로를 이용하여 조사하였다. 저항 값, poly-Si TFT의 문턱전압 및 이동도의 matching 조건을 디스플레이 시스템의 해상도에 따라 유도하였다. 또한, 소스 드라이버를 구현하기 위해 요구되는 poly-Si TFT의 유효 이동도를 다양한 패널 크기에 따라서 분석하였다. Using the existing analog circuits, required resistor matching and Poly-Si TFT characteristics are investigated for the implementation of analog circuits to be integrated on System-on-Glass. Matching requirements on resistor values, threshold voltage and mobility of poly-Si TFT are derived as a function of the resolution of display system. Also, the effective mobility of poly-Si TFT required for the realization of source driver is analyzed for various panel sizes.

Changes in the structure properties and CMP manufacturability of a poly-Si film induced by deposition and annealing processes

Park, S.,Jeong, H.,Yoon, S.H. Elsevier 2016 Journal of materials processing technology Vol.234 No.-

<P>A successful development of high-performance multilevel microdevices is attributed to the outstanding physical properties of a polycrystalline silicon (poly-Si) film which can be tailored by its process conditions. Here, we select deposition temperature and post-deposition annealing treatment as critical process parameters, followed by investigating their effects on both structure properties and chemical mechanical planarization (CMP) manufacturability of a poly-Si film. Experimental samples are prepared through low-pressure chemical vapor deposition (LPCVD) poly-Si deposition at different temperatures of 545-625 degrees C and thermal annealing treatment at 1050 degrees C under nitrogen atmosphere. At first, the poly-Si sample is inspected to characterize changes in macroscopic structure properties caused by the critical process parameters, together with changes in its surface morphology and grain boundary density. Next, the sample is polished to quantify changes in poly-Si CMP manufacturability such as material removal rate (MRR) and surface roughness. A relation between changes in microscopic features and changes in macroscopic properties is also discussed in depth. A poly-Si film deposited at 625 degrees C and then thermally annealed at 1050 degrees C shows significant improvement in both structure and CMP manufacturing aspects. The findings of this paper can potentially have a significant impact on developing poly-Si-based multilevel microdevices. (C) 2016 Elsevier B.V. All rights reserved.</P>

Three-Dimensional stacked CMOS Inverters Using Laser-Crystallized Poly-Si TFTs

이우현,정종완,오순영,안창근,조원주 한국물리학회 2009 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.54 No.5

High-performance three-dimensional (3-D) stacked poly-Si complementary metal-oxide- semi- conductor (CMOS) inverters with a high-quality laser-crystallized channel were fabricated. Low- temperature crystallization methods of an a-Si lm using excimer-laser annealing (ELA) and sequen- tial lateral solidification (SLS) were performed. The n-channel metal-oxide-semiconductor (NMOS) thin-film transistors (TFT) at the lower CMOS layer were fabricated on an oxidized bulk Si substrate and p-channel metal-oxide semiconductor (PMOS) TFT at the upper CMOS layer were fabricated on an interlayer dielectric film. Considerably uniform silicon grains were obtained by laser anneal- ing. Sub-threshold swings of the fabricated NMOS TFTs at the lower layer and PMOS TFTs at the upper layer were 78 mV/dec. and 86 mV/dec., respectively. The field effect mobilities of the NMOS and the PMOS TFTs were 42.5 cm2/V·s and 76 cm2/V·s, respectively. The on/offcurrent ratio of both TFTs was larger than 107. 3-D stacked poly-Si CMOS inverter showed excellent electrical characteristics and can be used the vertical integrated CMOS applications. High-performance three-dimensional (3-D) stacked poly-Si complementary metal-oxide- semi- conductor (CMOS) inverters with a high-quality laser-crystallized channel were fabricated. Low- temperature crystallization methods of an a-Si lm using excimer-laser annealing (ELA) and sequen- tial lateral solidification (SLS) were performed. The n-channel metal-oxide-semiconductor (NMOS) thin-film transistors (TFT) at the lower CMOS layer were fabricated on an oxidized bulk Si substrate and p-channel metal-oxide semiconductor (PMOS) TFT at the upper CMOS layer were fabricated on an interlayer dielectric film. Considerably uniform silicon grains were obtained by laser anneal- ing. Sub-threshold swings of the fabricated NMOS TFTs at the lower layer and PMOS TFTs at the upper layer were 78 mV/dec. and 86 mV/dec., respectively. The field effect mobilities of the NMOS and the PMOS TFTs were 42.5 cm2/V·s and 76 cm2/V·s, respectively. The on/offcurrent ratio of both TFTs was larger than 107. 3-D stacked poly-Si CMOS inverter showed excellent electrical characteristics and can be used the vertical integrated CMOS applications.