High Voltage SOL LDMOSFET의 최적 설계

이상용 우송대학교 1997 우송대학교 논문집 Vol.2 No.-

The analytical model necessary for designing the optimized SOI LDMOSFET is presented. To design an optimized SOI LDMOSFET, the effect of structural parameter on the breakdown mechanism should be analyzed. The breakdown voltage is calculated by finding the electric field in the channel and bulk regions. The criteria for the optimal design is determined based on the model suggested in this paper. The breakdown voltage calculated using the proposed model shows a good agreement with the results from DESSIS. the two dimensional device simulator for the structure of 300V SOI LDMOSFET. The results of this paper given an initial guess for the optimized SOI LDMOSFET design.

표면 도핑 기법을 사용한 SOI RESURF LDMOSFET의 항복전압 및 온-저항 특성 분석

김형우,김상철,방욱,강인호,김기현,김남균,Kim Hyoung-Woo,Kim Sang-Cheol,Bahng Wook,Kang In-Ho,Kim Kl-Hyun,Kim Nam-Kyun 한국전기전자재료학회 2006 전기전자재료학회논문지 Vol.19 No.1

In this paper, breakdown voltage and on-resistance characteristics of the surface doped SOI RESURF LDMOSFET were investigated as a function of surface doping depth. In order to verify the variation of characteristics, two-dimensional device simulation was carried out. Breakdown voltage of the proposed structure is varied from $73 {\~}138V$ while surface doping depth varied from $0.5{\~}2.0{\mu}m$. And on-resistance is decreased from $0.18{\~}0.143{\Omega}/cm^2$ while surface doping depth increased from $0.5 {\~}2.0{\mu}m$. Maximum breakdown voltage of the proposed structure is 138 V at $1.5{\mu}m$ depth of surface doping, yielding $22.1\%$ of improvement of breakdown voltage in comparison with that of the conventional SOI RESURF LDMOSFET with same epi-layer concentration. On-resistance characteristic is also improved about $21.7\%$.

스마트 파우어용 SOI LDMOSFET의 설계

이상용 우송대학교 1998 우송대학교 논문집 Vol.3 No.-

The analysis and simulation of 300V DMOSFET for smart power application has been performed. The effect of the device structural parameter on the breakdown and device performance was analyzed for optimal design. The design criteria for the high voltage DMOSFET was proposed and verified using the device simulator, DESSIS from ISE. The device structure for the LDMOSFET with 300V breakdown voltage was designed and verified using simulation. Finally the design methodology for the potimal structure of high voltage SOI LDMOSFET was proposed. The process condition was calculate based on independent thermal diffusion approximation and verified by the process and device simulation.

공정 및 설계 변수가 고전압 LDMOSFET의 전기적 특성에 미치는 영향

박훈수,이영기 한국전기전자재료학회 2004 전기전자재료학회논문지 Vol.17 No.9

In this study, the electrical characteristics of high-voltage LDMOSFET fabricated by the existing CMOS technology were investigated depending on its process and design parameter. In order to verify the experimental data, two-dimensional device simulation was carried out simultaneously. The off- state breakdown voltages of n-channel LDMOSFETs were increased nearly in proportional to the drift region length. For the case of decreasing n-well ion implant doses from $1.0\times{10}^{13}/cm^2$ to $1.0\times{10}^{12}/cm^2$, the off-state breakdown voltage was increased approximately two times. The on-resistance was also increased about 76 %. From 2-D simulation, the increase in the breakdown voltage was attributed to a reduction in the maximum electric field of LDMOS imolanted with low dose as well as to a shift toward n+ drain region. Moreover, the on- and off-state breakdown voltages were also linearly increased with increasing the channel to n-tub spacing due to the reduction of impact ionization at the drift region. The experimental and design data of these high-voltage LDMOS devices can widely applied to design smart power ICs with low-voltage CMOS control and high-voltage driving circuits on the same chip.

고효율 전력증폭기 설계를 위한 새로운 고조파 조절 회로 기반의 입출력 정합 회로

최재원(Jaewon Choi),서철헌(Chulhun Seo) 대한전자공학회 2009 電子工學會論文誌-TC (Telecommunications) Vol.46 No.2

본 논문에서는 새로운 고조파 조절 회로를 이용한 Si LDMOSFET 고효율 전력증폭기를 구현하였다. 본 고조파 조절 회로는 2차, 3차 고조파 성분에 대하여 단락 임피던스를 갖으며, 입출력 정합 회로를 설계하기 위하여 사용된다. 제안된 고조파 조절 회로의 효율 개선 효과가 class-F 혹은 inverse class-F 고조파 조절 회로 보다 우수하다는 것을 증명하였다. 또한, 고조파조절 회로가 출력 정합 회로뿐만 아니라, 입력 정합 회로에도 사용될 경우, 제안된 전력증폭기의 효율은 더욱 더 개선된다. 제안된 전력증폭기의 최대 전력 효율 (PAE)의 측정값은 1.71 GHz의 주파수 대역에서 82.68 %이다. Class-F와 inverse class-F 전력증폭기와 비교할 때, 제안된 전력증폭기의 최대 PAE 측정값은 5.08 ~ 9.91 % 향상된다. In this paper, a novel harmonic control circuit has been proposed for the design of high-efficiency power amplifier with Si LDMOSFET. The proposed harmonic control circuit having the short impedances for the second- and third-harmonic components has been used to design the in/output matching network. The efficiency enhancement effect of the proposed harmonic control circuit is superior to the class-F or inverse class-F harmonic control circuit. Also, when the proposed harmonic control circuit has been adapted to the input matching network as well as the output matching network, the efficiency enhancement effect of the proposed power amplifier has increased all the more. The measured maximum poweradded efficiency (PAE) of the proposed power amplifier is 82.68 % at 1.71 GHz band. Compared with class-F and inverse class-F amplifiers, the measured maximum PAE of the proposed power amplifier has increased in 5.08 ~ 9.91 %.

Electrical Characteristics of CMOS Circuit Due toChannel Region Parameters in LDMOSFET

김남수,이형규,Zhi-Yuan Cui,Kyoung-Won Kim 한국전기전자재료학회 2006 Transactions on Electrical and Electronic Material Vol.7 No.3

The electrical characteristics of CMOS inverter with LDMOSFET are studied for high power and digital circuit application by using two dimensional MEDICI simulator. The simulation is done in terms of voltage transfer characteristic and on-off switching properties of CMOS inverter with variation of channel length and channel doping levels. The channel which surrounds a junction-type source in LDMOSFET is considered to be an important parameter to decide a circuit operation of CMOS inverter. The digital logic levels of input voltage show to increase with increase of n-channel length and doping levels while the logic output levels show to the almost constant.

Effects of trench oxide and field plates on the breakdown voltage of SOI LDMOSFET

Hoon-Soo Park 한국물리학회 2010 Current Applied Physics Vol.10 No.2

To improve the breakdown voltage, we propose a SOI-based LDMOSFET with a trench structure in the drift region. Due to the trench oxide and underneath boron implanted layer, the surface electric field in the drift region effectively reduced. These effects resulted in the increment of breakdown voltage for the trenched LDMOS more than 100 V compared with the conventional device. However, the specific on-resistance, which has a trade-off relationship, is slightly increased. In addition to the trench oxide on the device performance, we also investigated the influence of n drift to n+ drain junction spacing on the off-state breakdown voltage. The measured breakdown voltages were varied more than 50 V with different n to n+ design spaces and achieved a maximum value at LDA = 2.0 ㎛. Moreover, the influence of field plate on the breakdown voltage of trench LDMOSFET was investigated. It is found that the optimum drain field plate over the field oxide is 8 ㎛.

Electrical Characteristics of a High-voltage P-channel LDMOSFET Utilizing SOI Technology

박훈수,Jin-Gun Koo,Sang-Gi Kim,Jin-Young Kang 한국물리학회 2009 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.55 No.3

In this paper, the electrical characteristics of a high-voltage p-channel LDMOSFET (lateral double-diffused metal oxide silicon field effect transistor) fabricated by using SOI technology are presented. The breakdown voltage characteristic of the p-LDMOS device, which depended on the drift layer length, was evaluated in detail. In order to optimize the electrical performance of a p-LDMOSFT having a thick gate oxide, we analyzed the influences of the p-drift junction formation and the drain and the gate field plates on the on- and off-state breakdown voltages. In this paper, the electrical characteristics of a high-voltage p-channel LDMOSFET (lateral double-diffused metal oxide silicon field effect transistor) fabricated by using SOI technology are presented. The breakdown voltage characteristic of the p-LDMOS device, which depended on the drift layer length, was evaluated in detail. In order to optimize the electrical performance of a p-LDMOSFT having a thick gate oxide, we analyzed the influences of the p-drift junction formation and the drain and the gate field plates on the on- and off-state breakdown voltages.

Electrical Characteristics of CMOS Circuit Due to Channel Region Parameters in LDMOSFET

Kim, Nam-Soo,Cui, Zhi-Yuan,Lee, Hyung-Gyoo,Kim, Kyoung-Won The Korean Institute of Electrical and Electronic 2006 Transactions on Electrical and Electronic Material Vol.7 No.3

The electrical characteristics of CMOS inverter with LDMOSFET are studied for high power and digital circuit application by using two dimensional MEDICI simulator. The simulation is done in terms of voltage transfer characteristic and on-off switching properties of CMOS inverter with variation of channel length and channel doping levels. The channel which surrounds a junction-type source in LDMOSFET is considered to be an important parameter to decide a circuit operation of CMOS inverter. The digital logic levels of input voltage show to increase with increase of n-channel length and doping levels while the logic output levels show to the almost constant.

Effect of Channel Length in LDMOSFET on the Switching Characteristic of CMOS Inverter

Cui, Zhi-Yuan,Kim, Nam-Soo,Lee, Hyung-Gyoo,Kim, Kyoung-Won The Korean Institute of Electrical and Electronic 2007 Transactions on Electrical and Electronic Material Vol.8 No.1

A two-dimensional TCAD MEDICI simulator was used to examine the voltage transfer characteristics, on-off switching properties and latch-up of a CMOS inverter as a function of the n-channel length and doping levels. The channel in a LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of a CMOS inverter. The digital logic levels of the output and input voltages were analyzed from the transfer curves and circuit operation. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.