RF 응용을 위한 플립칩 기술

이영민 한국마이크로전자및패키징학회 1999 마이크로전자 및 패키징학회지 Vol.6 No.4

통신분야에서 사용주파수대역의 증가, 제품의 소형화 및 가격경쟁력등의 요구에 따라 RF 소자의 패키징 기술도 플라스틱 패키지 대신에 flip chip interconnection, MCM(multichip module)등과 같은 고밀도 실장기술이 발전해가고 있다. 따라서, 본 논문은 최근 수년간 보고된 응용사례를 중심으로 RF flip chip의 기술적인 개발방향과 장점들을 분석하였고, RF 소자 및 시스템의 개발단계에 따른 적합한 적용기술을 제시하였다. RF flip chip의 기술동향을 요약하면, 1) RF chip배선은 microstrip 대신에 CPW 구조을 선택하며, 2) wafer back-side grinding을 하지 않아서 제조공정이 단순하고 wafer 파손이 적어 제조비용을 낮출 수 있고, 3) wire bonding 패키징에 비해 전기적인 특성이 우수하고 고집적의 송수신 모듈개발에 적합하다는 것이다. 그러나, CPW 배선구조의 RF flip chip 특성에 대한 충분한 연구가 필요하며 RF flip chip의 초기 개발 단계에서 flip chip interconnection 방법으로는 Au stud bump bonding이 적합할 것으로 제안한다. The recent trend toward higher frequencies, miniaturization and lower-cost in wireless communication equipment is demanding high density packaging technologies such flip chip interconnection and multichip module(MCM) as a substitute of conventional plastic package. With analyzing the recently reported research results of the RF flip chip, this paper presents the technical issues and advantages of RF flip chip and suggest the flip chip technologies suitable for the development stage. At first, most of RF flip chips are designed in a coplanar waveguide line instead of microstrip in order to achieve better electrical performance and to avoid the interaction with a substrate. Secondly, eliminating wafer back-side grinding, via formation, and back-side metallization enables the manufacturing cost to be reduced. Finally, the electrical performance of flip chip bonding is much better than that of plastic package and the flip chip interconnection is more suitable for Transmit/Receiver modules at higher frequency. However, the characterization of CPW designed RF flip chip must be thoroughly studied and the Au stud bump bonding shall be suggested at the earlier stage of RF flip chip development.

웨어러블 디바이스용 Flip-chip 기반 마이크로LED 디스플레이 광원 모듈 연구

백준승,유경선,현동훈 국제차세대융합기술학회 2021 차세대융합기술학회논문지 Vol.5 No.5

본 논문에서는 웨어러블 디바이스용 SVGA급(800×600 pixel) Flip-chip 기반의 마이크로 LED 디스플레 이 광원 모듈 연구를 통해 마이크로LED 제작 공정을 개선하고, 시제품의 성능을 측정하여, 제품의 상용화 가능성 을 분석하였다. 먼저, 800×600 Flip-chip 기반 마이크로LED 어레이와 PM 구동 평가를 위해 32×32 어레이를 설 계 및 제작하여, 그 성능 및 제품화의 가능성을 확인하였으며, 제작 공정 기술에서 Self align 전극 형성 기술과 고집적화 어레이의 Mesa 형성을 위한 드라이 에칭 기술을 적용하여 생산성을 향상하였다. 본 연구를 기반으로 추 후 마이크로LED가 제품화시 향후 플렉서블 디스플레이 뿐만이 아닌 다양한 분야에서 적용 가능함으로 관련 산업 으로의 파급효과가 클 것으로 예상된다. In this paper, we try to analyze the commercial potential of products by improving the micro-LED manufacturing process and measuring the performance of prototypes through research on the SVGA-class (800×600 pixel) flip-chip-based micro LED display light module for wearable devices. First, the 800×600 flip-chip based microLED array and the 32×32 array were designed and manufactured for PM driving evaluation, and their performance and potential for commercialization were confirmed. Productivity was improved by applying dry etching technology to form Mesa. Based on this study, when microLED is commercialized in the future, it is expected to have a large ripple effect on related industries as it can be applied to various fields as well as flexible displays in the future.

X선을 이용한 플립칩 접합부 비파괴 검사 방법의 표준화

송현준,김주현 표준인증안전학회 2018 표준인증안전학회지 Vol.8 No.4

Electronics and communication technology have become important throughout most of the current manufacturing industry. Additionally, there is a trend to minimize product size while making the external shape and functions more digitally converging and higher speed. Therefore, high quality semiconductor technology is required, particularly in the rising importance of packaging technology to increase mounting efficiency per unit volume. Packaging technology has been researched and utilized by categorizing it into wire bonding, TAB bonding, and flip-chip bonding. Currently, the most universally used form is wire bonding, but in order to achieve lighter and smaller packaging, flip-chip technology is the key. Since flip-chip technology involves solder bump bonding in the area where the chip is connected to the board rather than using wire or lead, chip scale packaging is possible and it possesses the shortest bond length, lower thermal resistance, a lower dielectric constant (k), and a particularly high strength in stack packaging technology. We executed nondestructive inspection that uses X-ray for bonding of the flip-chip and could extract intensity distribution map using information of each pixel from the X-ray image of flip -chip. Comparing each extracted intensity distribution map with the standard intensity distribution map (optimally intensity distribution map of most suitable bonded solder bump of flip chip), we can detect bad bonding (hole or bridge) and over wetting of the flip-chip. Also, it can extract each solder bump shape(edge) by analyzing intensity data, and can determine bonding state analyzing intensity value through comparison with CAD data. 플립칩 기술은 접합기술 이상으로 검사기술이 중요하다. 현재 2차원이나 3차원 형상 및 치수측정으로 가장 일반적으로 사용되는 레이저 및 시각에 의한 검사 측정 기술은 외부의 조명에 대하여 대상 물체의 표면이 반사광에 의하여 상을 얻는 것이므로, 조명 조건이나 대상 물체의 표면 반사 특성에 의하여 영상의 특성이 민감하게 변화되고, 특히 표면이 정반사 성분이 강한 경우 대상 물체의 자세 변화에 따라 영상에 큰 변화가 있기 때문에 대상 물체 표면의 반사 특성에 따른 신뢰성 문제를 가진다. 또한 대상 물체의 표면에 대한 정보만을 얻을 수 있으므로, 다른 물체에 의해 가려지거나 내부에 존재하는 부분에 대한 정보는 얻을 수가 없는 제약이 있어 플립칩과 같이 전기적 연결 부위가 내부로 감추어진 형태의 반도체 검사에는 적합하지 못하다. 본 연구에서는 X선 영상을 사용함으로써 위의 시각 검사를 사용한 방법의 제약점들을 극복할 수 있다. X선 시스템은 고가의 장비가 필요하고, 안전의 문제로 인하여 주로 의료용에서 사용되어 왔으나, 산업 현장에서 카메라 센서로 가시화될 수 없는 반도체 내부 부품의 검사 및 측정을 위한 대안으로 활용도가 높아지고 있다. 따라서 이와 같은 시스템을 활용하여 반도체 내부 부품의 검사 방법을 표준화하여 신뢰성 제품 개발을 할 수 있다.

신축성 전자패키징을 위한 CNT-Ag 복합패드에서의 플립칩 공정

최정열,오태성,Choi, Jung Yeol,Oh, Tae Sung 한국마이크로전자및패키징학회 2013 마이크로전자 및 패키징학회지 Vol.20 No.4

As a basic research to develop stretchable electronic packaging technology, CNT-Ag composite pads were formed on top of Cu/Sn chip bumps and flip-chip bonded using anisotropic conductive adhesive. Average contact resistances of the flip-chip joints were measured with respect to bonding pressure and presence of the CNT-Ag composite pads. When Cu/Sn chip bumps with CNT-Ag composite pads were flip-chip bonded to substrate Cu pads at 25MPa or 50 MPa, contact resistance was too high to measure. The specimen processed by flip-chip bonding the Cu/Sn chip bumps with CNT-Ag composite pads to the substrate Cu pads exhibited an average contact resistance of $213m{\Omega}$. On the other hand, the flip-chip specimens processed by bonding Cu/Sn chip bumps without CNT-Ag composite pads to substrate Cu pads at 25MPa, 50MPa, and 100MPa exhibited average contact resistances of $370m{\Omega}$, $372m{\Omega}$, and $112m{\Omega}$, respectively. 신축성 전자패키징 기술개발을 위한 기초연구로서 Cu/Sn 범프에 CNT-Ag 복합패드를 형성한 칩을 이방성 전도접착제를 사용하여 플립칩 본딩한 후, CNT-Ag 복합패드의 유무 및 본딩압력에 따른 플립칩 접속부의 접속저항을 측정하였다. CNT-Ag 복합패드가 형성된 Cu/Sn 칩 범프를 25MPa과 50MPa의 본딩압력으로 플립칩 본딩한 시편들은 접속저항이 너무 높아 측정이 안되었으며, 100MPa의 본딩압력으로 플립칩 본딩한 시편은 $213m{\Omega}$의 평균 접속저항을 나타내었다. 이에 비해 CNT-Ag 복합패드가 없는 Cu/Sn 칩 범프를 사용하여 25MPa, 50 MPa 및 100 MPa의 본딩압력으로 플립칩 본딩한 시편은 각기 $1370m{\Omega}$, $372m{\Omega}$ 및 $112m{\Omega}$의 평균 접속저항을 나타내었다.

Flip-Chip Process using Heat Transfer from an Induction-Heating Film

오태성,이광용,이윤희,정부양 대한금속·재료학회 2009 METALS AND MATERIALS International Vol.15 No.3

A new flip-chip technology to attach an IC chip directly to a substrate was studied using the heat transfer from an induction-heating film in an AC magnetic field. When applying a magnetic field of 230 Oe at 14 kHz, the temperature of a 600 μm-thick 5 mm × 5 mm Cu induction-heating film reached 250 °C within 60 s. The temperature of the glass substrate used in this process was kept below 118 °C at a distance of 1,350 μm from the Cu induction-heating film, which was maintained at 250 °C, implying that damage to a substrate can be minimized with the flip-chip process using heat transfer from an induction-heating film. Flip-chip bonding was successfully accomplished with the reflow of Sn-3.5Ag solder bumps by applying a magnetic field of 230 Oe at 14 kHz for 120 s to a Cu induction-heating film. A new flip-chip technology to attach an IC chip directly to a substrate was studied using the heat transfer from an induction-heating film in an AC magnetic field. When applying a magnetic field of 230 Oe at 14 kHz, the temperature of a 600 μm-thick 5 mm × 5 mm Cu induction-heating film reached 250 °C within 60 s. The temperature of the glass substrate used in this process was kept below 118 °C at a distance of 1,350 μm from the Cu induction-heating film, which was maintained at 250 °C, implying that damage to a substrate can be minimized with the flip-chip process using heat transfer from an induction-heating film. Flip-chip bonding was successfully accomplished with the reflow of Sn-3.5Ag solder bumps by applying a magnetic field of 230 Oe at 14 kHz for 120 s to a Cu induction-heating film.

Strain behaviors of solder bump with underfill for flip chip package under thermal loading condition

곽재 대한기계학회 2014 JOURNAL OF MECHANICAL SCIENCE AND TECHNOLOGY Vol.28 No.12

Since the introduction of Cu/low-k as the interconnect material, the chip-package interaction (CPI) has become a critical reliabilitychallenge for flip chip packages. Revision of underfill material must be considered, which compromises the life of flip chip interconnectby releasing the stresses transferred to the silicon devices from the solder bumps, and thereby maintain the overall package reliability. Thus, it is important to understand the thermo-mechanical behavior of solder bumps. In this study, the solder bump reliability in flip chippackage was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermomechanicalbehavior of solder joints, especially the solder bumps located at the chip corners where most failures usually occur was investigated. Digital image correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strainsof cross-sectioned solder bump of flip-chip package subjected to thermal loading from 25°C to 100°C. The results clearly show captureddeformations of solder bump under thermal loading. Finally, finite element analysis (FEA) was conducted by simulating the thermalloading applied in the experiments, and validated with experimental results. Then, consistently using the FEA analysis, parametric studyfor underfill material properties were performed on the reliability of flip chip package, by varying the glass transition temperature (Tg),Young’s modulus (E), and coefficient of thermal expansion (CTE). Averaged plastic work of the corner solder bump and stress at the dieside were obtained and used as damage indicators for solder bumps and low-k dielectrics layer, respectively. The results show that highTg, and E of underfill are generally desirable to improve the reliability of solder interconnects in the flip chip package.

새로운 칩온칩 플립칩 범프 접합구조에 따른 초고주파 응답 특성

오광선(Kwang-Sun Oh),이상경(Sang-Kyung Lee),김동욱(Dong-Wook Kim) 한국전자파학회 2013 한국전자파학회논문지 Vol.24 No.12

본 논문에서는 칩온웨이퍼(Chip on Wafer: CoW) 공정기술을 이용한 새로운 칩온칩(Chip on Chip: CoC) 플립칩 범프 구조들을 제안하여 설계, 제작하고, 초고주파 영역에서의 응답 특성을 분석하였다. Cu 필러(Pillar)/SnAg, Cu 필러/Ni/SnAg의 기존 범프들, 그리고 SnAg, Cu 필러/SnAg, Cu 필러/Ni/SnAg를 Polybenzoxazole(PBO)로 보호한 새로운 범프들을 구성하여 웨이퍼의 2<SUP>nd</SUP> Polyimide(PI2) 층의 도포 유무에 따라 10가지 형태의 CoC 샘플들을 구조 설계하였고, 20 GHz까지의 주파수 특성이 고찰되었다. 측정 결과를 고려할 때 PI2 층이 도포된 소자들이 본 실험에 사용된 배치 플립칩 공정에 더 적합함을 알 수 있었고, 18 GHz에서 평균 0.14 dB의 삽입 손실을 보였다. 미세 패드 간격을 가지는 칩의 패키지 용도로 새로 개발된 범프들의 삽입 손실(0.11~0.14 dB)은 기존 범프들의 삽입 손실(0.13~0.17 dB)과 비교해 18 GHz까지 유사한 성능을 보이거나, 다소 좋은 특성을 보여 높은 집적도를 요구하는 다양한 초고주파 패키지에 활용될 수 있음이 확인되었다. In this paper, novel chip-on-chip(CoC) flip-chip bump structures using chip-on-wafer(CoW) process technology are proposed, designed and fabricated, and their microwave frequency responses are analyzed. With conventional bumps of Cu pillar/SnAg and Cu pillar/Ni/SnAg and novel Polybenzoxazole(PBO)-passivated bumps of Cu pillar/SnAg, Cu pillar/Ni/SnAg and SnAg with the deposition option of 2<SUP>nd</SUP> Polyimide(PI2) layer on the wafer, 10 kinds of CoC samples are designed and their frequency responses up to 20 GHz are investigated. The measurement results show that the bumps on the wafers with PI2 layers are better for the batch flip-chip process and have average insertion loss of 0.14 dB at 18 GHz. The developed bump structures for chips with fine-pitch pads show similar or slightly better insertion loss of 0.11~0.14 dB up to 18 GHz, compared with that of 0.13~0.17 dB of conventional bump structures in this study, and we find that they could be utilized in various microwave packages for high integration density.

플립칩에서 솔더볼의 매개변수 변화에 따른 동적 해석 평가

김성걸(Kim SeongKeol),김한중(Kim HanJung),임승영(Lim SeungYoung),김순영(Kim SoonYoung),양인영(Yang InYoung),안은진(An EunJin) 한국생산제조학회 2010 한국생산제조시스템학회 학술발표대회 논문집 Vol.2010 No.10

Drop impact reliability assessment of solder joints on the Flip chip is one of the critical issues for growing use in the handheld products and environmental concerns. Our previous research has been showing that new solder ball compositions of Sn-3.0Ag-0.5Cu has better mechanical reliability than Sn-1.0Ag-0.5Cu. In this paper, Dynamic reliability analysis using Finite Element Analysis (FEA) is carried out to assess the factors affecting flip chip in drop reliability. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.2Ag0.5Cu. The board systems by JEDEC standard including 15 chips, solder balls and PCB are modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder bumps. It is found that larger chip size, smaller chip array, smaller ball diameter, larger pitch, and larger chip thickness have bad effect on maximum yield stress and strain at solder ball of each chip.

Designing A Particular Flip Chip Structure Aimed For Electromigration Reduction Using Finite Element Method

Vipa Rungyusiri,Chiranut Sa-ngiamsak,Sanchai Harnsoongnoen,Poonsak Intarakul 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7

A reliability performance is the major concern for flip chip solder joint. The electromigration behaviors of lead free (Sn4.0Ag0.5Cu) flip chip solder joint made with Cu, Al trace and with Cu and Ni underbump metallurgy on the chip under current stressing were carefully studied. The simulation results show that Cu trace provides lifetime of 24% longer than Al trace. Moreover, by adding UBM into the flip-chip structure even increases the lifetime to failure upto 25% in case of Ni UBM and 32% in case of Cu UBM. In another word, the simulations clearly validate that the time to failure of flip chip solder joint with Cu trace structure and with Cu UBM is approximately 32% longer than that of none UBM structure. In conclusion, Cu is the suitable material for trace and UBM of flip chip solder joint structure in a lifetime to failure aspect.

플립칩에서 솔더볼의 매개변수 변화에 따른 동적 해석 평가

김성걸(Kim SeongKeol),김한중(Kim HanJung),임승영(Lim SeungYoung),김순영(Kim SoonYoung),양인영(Yang InYoung),안은진(An EunJin) 한국생산제조학회 2010 한국공작기계학회 추계학술대회논문집 Vol.2010 No.-

Drop impact reliability assessment of solder joints on the Flip chip is one of the critical issues for growing use in the handheld products and environmental concerns. Our previous research has been showing that new solder ball compositions of Sn-3.0Ag-0.5Cu has better mechanical reliability than Sn-1.0Ag-0.5Cu. In this paper, Dynamic reliability analysis using Finite Element Analysis (FEA) is carried out to assess the factors affecting flip chip in drop reliability. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.2Ag0.5Cu. The board systems by JEDEC standard including 15 chips, solder balls and PCB are modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder bumps. It is found that larger chip size, smaller chip array, smaller ball diameter, larger pitch, and larger chip thickness have bad effect on maximum yield stress and strain at solder ball of each chip.