1.42-3.97㎓ 디지털 제어 방식 LC 발진기의 설계

이종석,문용 大韓電子工學會 2012 電子工學會論文誌-SD (Semiconductor and devices) Vol.49 No.7

디지털 PLL의 핵심블록이 되는 디지털 제어 발진기를 LC 구조를 기반으로 설계하고 0.18㎛ RF CMOS 공정을 사용하여 제작하였다. 2개의 교차쌍 구조의 NMOS 코어를 이용하여 광대역 특성을 구현하였으며, PMOS 배랙터쌍을 이용하여 수 aF의 작은 캐패시터값의 변화를 얻을 수 있었다. 캐패시터 축퇴 기법을 사용하여 캐패시턴스 값을 감소시키어 고해상도 주파수 특성을 구현하였다. 또한, 노이즈 필터링 기법을 바이어스 회로 등에 적용하여 위상잡음에 강한 구조로 설계를 하였다. 측정결과 중심주파수 2.7㎓에서 2.5㎓의 주파수 대역의 출력이 가능하였으며 2.9 ~ 7.1㎑의 높은 주파수해상도를 얻을 수 있었다. 미세 튜닝범위와 코어의 전류 바이어스는 4개의 PMOS 배열을 통하여 제어가 가능하도록 하여 유연성을 높였다. 1.8V 전원에서 전류는 17~26㎃ 정도를 소모하였다. 설계한 DCO는 다양한 통신시스템에 응용이 가능하다. The LC-based digitally controlled oscillator (LC-DCO), a key component of the all digital phase locked loop (ADPLL), is designed using 0.18 ㎛ RFCMOS process with 1.8 V supply. The NMOS core with double cross-coupled pair is chosen to realize wide tuning range, and the PMOS varactor pair that has small capacitance of a few aF and the capacitive degeneration technique to shrink the capacitive element are adopted to obtain the high frequency resolution. Also, the noise filtering technique is used to improve phase noise performance. Measurement results show the center frequency of 2.7 ㎓, the tuning range of 2.5 ㎓ and the high frequency resolution of 2.9 ㎑ ~7.1 ㎑. Also the fine tuning range and the current consumption of the core could be controlled by using the array of PMOS transistors using current biasing. The current consumption is between 17 ㎃ and 26 ㎃ at 1.8V supply voltage. The proposed DCO could be used widely in various communication system.

Low-Power, All Digital Phase-Locked Loop with a Wide-Range, High Resolution TDC

YoungGun Pu,AnSoo Park,Joon-Sung Park,이강윤 한국전자통신연구원 2011 ETRI Journal Vol.33 No.3

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 mm2 using 0.13 μm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is –120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

능동 인덕터를 이용한 광대역 디지털 제어 발진기의 설계

부영건(YoungGun Pu),박안수(AnSoo Park),박형구(HyungGu Park),박준성(Joon-Sung Park),이강윤(Kang-Yoon Lee) 大韓電子工學會 2011 電子工學會論文誌-SD (Semiconductor and devices) Vol.48 No.3

본 논문은 넓은 튜닝 범위와 정밀한 해상도 성능을 가지는 능동 인덕터를 이용한 디지털 제어 발진기에 대한 논문이다. 디지털 제어 발진기의 주파수를 조정하기 위해 능동 인덕터의 트랜스컨덕턴스를 디지털적으로 조정하는 구조를 제안하였으며, 디지털 제어 발진기의 이득 또한 디지털적으로 조정하여 이득 변화를 상쇄하도록 하였다. 또한, 넓은 튜닝 영역과 정밀한 해상도를 구현하기 위해 자동 3 단계 주파수 및 이득 튜닝 루프를 제안하였다. 디지털 제어 발진기의 총 주파수 튜닝 영역은 2.1㎓~3.5㎓로 1.4㎓의 영역으로 이는 2.4㎓의 중간 주파수에 대하여 58 %에 해당한다. 유효 주파수 해상도는 시그마 델타 모듈레이터를 사용하여 0.14 ㎑/LSB를 구현하였다. 제안하는 디지털 제어 발진기는 0.13 ㎛ CMOS 공정으로 설계 되었다. 전체 전력 소모는 1.2 V 공급전압에서 6.6 ㎽이며 위상 잡음 성능은 2.4 ㎓ 중간 주파수의 경우, 1 ㎒ 오프셋에서 -120.67 ㏈c/㎐ 성능을 보이고 있다. This paper presents a wide tuning range, fine-resolution DCO (Digitally Controlled Oscillator) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. To cover the wide tuning range, an automatic three-step coarse tuning scheme is proposed. The DCO total frequency tuning range is 1.4 ㎓ (2.1 ㎓ to 3.5 ㎓), it is 58 % at 2.4 ㎓. An effective frequency resolution is 0.14 ㎑/LSB. The proposed DCO is implemented in 0.13 μm CMOS process. The total power consumption is 6.6 ㎽ from a 1.2 V supply voltage. The phase noise of the DCO output at 2.4 ㎓ is -120.67 ㏈c/Hz at 1 ㎒ offset.

저면적 디지털 제어 발진기의 양자화 에러 최소화를 위한추가 서모미터 코드 잠금 기법

강병석,김영식,김신웅 한국전기전자학회 2023 전기전자학회논문지 Vol.27 No.4

This paper introduces a new locking technique applicable to high-performance digital Phase-Locked Loops(DPLL). The study employs additional thermometer codes to reduce quantization errors in LC-based DigitalControlled Oscillators (DCO). Despite not implementing the entire DCO codes in thermometer mode, this methodeffectively reduces quantization errors through enhanced linearity. In the initial locking phase, binary codes areused, and upon completion of locking, the system transitions to thermometer codes, achieving high frequencylinearity and reduced jitter characteristics. This approach significantly reduces the number of switches requiredand minimizes the oscillator's area, especially in applications requiring low DCO gain (Kdco), compared to thetraditional method that uses only thermometer codes. Furthermore, the jitter performance is maintained at a levelequivalent to that of the thermometer-only approach. The efficacy of this technique has been validated throughmodeling and design at the RTL level using SystemVerilog and Verilog HDL

Design of a 12 to 14.5 GHz Digitally-Controlled Oscillator for an Ultra-Low-Jitter PLL

방주은,조용우,최서진,최재혁 한국과학기술원 반도체설계교육센터 2021 IDEC Journal of Integrated Circuits and Systems Vol.7 No.1

A DCO was designed for an ultra-low-jitter digital sub-sampling PLL. To suppress the enormous amount of quantization noise, a very fine frequency resolution is critical. Also, the phase noise of an LC VCO itself is crucial for ultra-low-jitter applications. For high-performance LC VCO design, a basic insight into the oscillator is needed. The proposed DCO consists of a string-type RDAC, MASH 1-1 DSM, and CMOS-type cross-coupled LC VCO. The frequency resolution is significantly increased by using the DSM. The proportional path has a 17-bit resolution, while the integral path has an 18-bit resolution. The DSM operates at 400 MHz, and its quantization noise is canceled by the 2nd-order low-pass filter at the output of the DAC. By adopting 2nd-order noise shaping, the quantization noise at the PLL output is negligible. The DAC was designed with a string resistor topology for its design simplicity and relieved target specifications. The DCO has a 12 to 14.5 GHz frequency tuning range. The phase noise at a 1 MHz offset frequency is –109 dBc/Hz at a 14-GHz output. The average power consumption is 5.5 mW. The calculated FOM at a 1-MHz offset frequency is –184.5 dB.

Wide-Band Fine-Resolution DCO with an Active Inductor and Three-Step Coarse Tuning Loop

YoungGun Pu,AnSoo Park,Joon-Sung Park,Yeon-Kug Moon,김석기,이강윤 한국전자통신연구원 2011 ETRI Journal Vol.33 No.2

This paper presents a wide-band fine-resolution digitally controlled oscillator (DCO) with an active inductor using an automatic three-step coarse and gain tuning loop. To control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO tuning range is 58% at 2.4 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The phase noise of the DCO output at 2.4 GHz is –120.67 dBc/Hz at 1 MHz offset.

A 1Gbps reference-less clock and data recovery using injection phase locked loop

진수완,Chang Zhi Yu,이대웅,범진욱 한국과학기술원 반도체설계교육센터 2018 IDEC Journal of Integrated Circuits and Systems Vol.4 No.3

Injection Locking Phase-Locked Loop (IL-PLL) technique applied to 0.7 ~ 1.3Gb/s Clock and Data Recovery (CDR) is presented in this paper. Conventional CDR implemented by adding a Frequency Locked Loop (FLL) in a PLL in order to achieve a sufficiently large dynamic range. The proposed structure achieves wide input data rate range and low power consumption by implementing a FLL with digital circuits. A PLL to recover the clock and data was implemented digitally. The advantage of digital circuit design is a small area, low power and the ease of re-design. The proposed reference-less CDR is implemented in Magna Foundry 0.18um CMOS process. The measurement result is that the phase noise is about -108.57dBc/Hz at 1Mhz offset. The area of chip is a 0.55〖mm〗^2 and the power consumption with 1.8V supply voltage is 17.5mW when CDR operate at 1Gb/s of input data stream.

A PVT-compensated 2.2 to 3.0 GHz Digitally Controlled Oscillator for All-Digital PLL

Anil Kavala,배우람,김성우,Gi-Moon Hong,Han-Kyu Chi,김수환,정덕균 대한전자공학회 2014 Journal of semiconductor technology and science Vol.14 No.4

We describe a digitally controlled oscillator (DCO) which compensates the frequency variations for process, voltage, and temperature (PVT) variations with an accuracy of ±2.6% at 2.5 GHz. The DCO includes an 8 phase current-controlled ring oscillator, a digitally controlled current source (DCCS), a process and temperature (PT)-counteracting voltage regulator, and a bias current generator. The DCO operates at a center frequency of 2.5 GHz with a wide tuning range of 2.2 GHz to 3.0 GHz. At 2.8 GHz, the DCO achieves a phase noise of -112 dBc/Hz at 10 MHz offset. When it is implemented in an all-digital phase-locked loop (ADPLL), the ADPLL exhibits an RMS jitter of 8.9 ps and a peak to peak jitter of 77.5 ps. The proposed DCO and ADPLL are fabricated in 65 nm CMOS technology with supply voltages of 2.5 V and 1.0 V, respectively.

A PVT-compensated 2.2 to 3.0 GHz Digitally Controlled Oscillator for All-Digital PLL

Kavala, Anil,Bae, Woorham,Kim, Sungwoo,Hong, Gi-Moon,Chi, Hankyu,Kim, Suhwan,Jeong, Deog-Kyoon The Institute of Electronics and Information Engin 2014 Journal of semiconductor technology and science Vol.14 No.4

We describe a digitally controlled oscillator (DCO) which compensates the frequency variations for process, voltage, and temperature (PVT) variations with an accuracy of ${\pm}2.6%$ at 2.5 GHz. The DCO includes an 8 phase current-controlled ring oscillator, a digitally controlled current source (DCCS), a process and temperature (PT)-counteracting voltage regulator, and a bias current generator. The DCO operates at a center frequency of 2.5 GHz with a wide tuning range of 2.2 GHz to 3.0 GHz. At 2.8 GHz, the DCO achieves a phase noise of -112 dBc/Hz at 10 MHz offset. When it is implemented in an all-digital phase-locked loop (ADPLL), the ADPLL exhibits an RMS jitter of 8.9 ps and a peak to peak jitter of 77.5 ps. The proposed DCO and ADPLL are fabricated in 65 nm CMOS technology with supply voltages of 2.5 V and 1.0 V, respectively.

디지털 제어 발진기의 전력소모 최적화 설계기법

이두찬(Doo-Chan Lee),김규영(Kyu-Young Kim),김수원(Soo-Won Kim) 大韓電子工學會 2010 電子工學會論文誌-SD (Semiconductor and devices) Vol.47 No.5

본 논문에서는 디지털 제어 발진기의 전력소모를 최적화하는 설계기법을 제안한다. 디지털 제어 발진기의 Coarse tuning 비트수와 Fine tuning 비트수를 조절하여 LSB Resolution, 주파수 범위, 선형성, 이식성에는 영향을 주지 않고 전력소모를 최적화한다. 이를 위해 제어 비트에 따른 디지털 제어 발진기의 전력소모 변화를 분석하였다. 본 논문에서는 0.13㎛ 1.2V CMOS 라이브러리를 이용하여 제안한 설계기법을 적용한 경우와 그렇지 않은 경우를 모두 설계, 모의실험 및 검증하였다. 제안한 설계기법을 적용한 디지털 제어 발진기는 모의실험결과 283㎒부터 1.1㎓의 클록을 생성할 수 있으며, LSB Resolution은 1.7㎰이다. 디지털 제어 발진기의 출력 주파수가 1㎓일 때 전력소모는 2.789㎽이다. This paper presents a design procedure of digitally controlled oscillator(DCO) for power optimization. By controlling coarse tuning bits and fine tuning bits of DCO, the proposed design procedure can optimize the power dissipation and does not affect the LSB resolution, frequency range, linearity, portability. For optimization, the relationship between control bits and power dissipation of the DCO was analyzed. The DCO circuits using and unusing proposed design technique have been designed, simulated and proved using 0.13㎛, 1.2V CMOS library. The DCO circuit with proposed design technique has operation range between 283㎒ and 1.1㎓ and has 1.7㎰ LSB resolution and consumes 2.789㎽ at frequency of 1㎓.