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Fluorine 주입에 따른 NMOSFET의 소자 특성 연구
권성규,권혁민,이환희,장재형,곽호영,고성용,이원묵,이성재,이희덕,Kwon, Sung-Kyu,Kwon, Hyuk-Min,Lee, Hwan-Hee,Jang, Jae-Hyung,Kwak, Ho-Young,Go, Sung-Yong,Lee, Weon-Mook,Lee, Song-Jae,Lee, Hi-Deok 한국전기전자재료학회 2012 전기전자재료학회논문지 Vol.25 No.1
In this paper, we investigated the device performance on fluorine implantation, hot carrier reliability and RTS (random telegraph signal) noise characteristics of NMOSFETs. The capacitance of the fluorine implanted NMOSFET decreased due to the increase of the gate oxide thickness. RTS noise characteristics of the fluorine implated NMOSFET was improved approximately by 46% due to the decrease of trap density at Si/$SiO_2$ interface. The improved gate oxide quality also results in the longer hot carrier life time.
0V 턴 오프 MOS Controlled Thyristor 소자 구조 설계 및 전압전류특성 시뮬레이션
권성규(Sung-Kyu Kwon),조두형(Doo-Hyung Cho),원종일(Jong-Il Won),장현규(Hyun-Gyu Jang),정동윤(Dong-Yun Jung),박건식(Kun-Sik Park) 대한전자공학회 2020 대한전자공학회 학술대회 Vol.2020 No.11
Current driving capability is one of the important specifications in MCT (MOS Controlled Thyristor) which is determined by turn-off characteristics. Meanwhile, high peak anode current and di/dt are related to the turn-on characteristics. Thus, both on-FET and off-FET performance need to be improved. In this paper, the structure of MCT with the off-FET which is turned on at the gate voltage of 0V by forming a “depletion mode off-FET channel region” in a part of the off-FET channel region of the unit cell of an MCT device is presented. The MCT is turned on at an arbitrary gate voltage and turned off at a gate voltage of 0V with adjusting the ion implantation condition. This demonstrates that the turn-on and turn-off characteristics of the MCT are enhanced and can be simplify the gate driving circuit.
PMOSFET의 채널 길이에 따른 NBTI 스트레스와 CHC 스트레스의 신뢰성 특성 비교 분석
유재남,권성규,신종관,오선호,장성용,송형섭,이가원,이희덕,Yu, Jae-Nam,Kwon, Sung-Kyu,Shin, Jong-Kwan,Oh, Sun-Ho,Lee, Ho-Ryung,Jang, Sung-Yong,Song, Hyung-Sub,Lee, Ga-Won,Lee, Hi-Deok 한국전기전자재료학회 2014 전기전자재료학회논문지 Vol.27 No.7
Channel length dependence of NBTI (negative bias temperature instablilty) and CHC (channel hot carrier) characteristics in PMOSFET is studied. It has been considered that HC lifetime of PMOSFET is larger than NBTI lifetime. However, it is shown that CHC degradation is greater than NBTI degradation for PMOSFET with short channel length. 1/f noise and charge pumping measurement are used for analysis of these degradations.
65 nm CMOS 기술에서 소자 종류에 따른 신뢰성 특성 분석
김창수,권성규,유재남,오선호,장성용,이희덕,Kim, Chang Su,Kwon, Sung-Kyu,Yu, Jae-Nam,Oh, Sun-Ho,Jang, Seong-Yong,Lee, Hi-Deok 한국전기전자재료학회 2014 전기전자재료학회논문지 Vol.27 No.12
In this paper, we investigated the hot carrier reliability of two kinds of device with low threshold voltage (LVT) and regular threshold voltage (RVT) in 65 nm CMOS technology. Contrary to the previous report that devices beyond $0.18{\mu}m$ CMOS technology is dominated by channel hot carrier(CHC) stress rather than drain avalanche hot carrier(DAHC) stress, both of LVT and RVT devices showed that their degradation is dominated by DAHC stress. It is also shown that in case of LVT devices, contribution of interface trap generation to the device degradation is greater under DAHC stress than CHC stress, while there is little difference for RVT devices.
RF 인덕터의 Underpass에 따른 품질 계수 및 항복전압 특성
신종관,권성규,장성용,정진웅,유재남,오선호,김철영,이가원,이희덕,Shin, Jong-Kwan,Kwon, Sung-Kyu,Jang, Sung-Yong,Jung, Jin-Woong,Yu, Jae-Nam,Oh, Sun-Ho,Kim, Choul-Young,Lee, Ga-Won,Lee, Hi-Deok 한국전기전자재료학회 2014 전기전자재료학회논문지 Vol.27 No.6
In this paper, the effect of underpass structure on quality factor and breakdown voltage of octagonal inductors which were fabricated with 90 nm complementary metal-oxide-semiconductor (CMOS) technology for radio frequency integrated circuit (RFIC) was studied. It was found that quality factor and breakdown voltage of inductors with more than one metal layer for underpass showed improved properties compared to those with one metal layer. However, little change of quality factor and breakdown voltage was observed between the inductors with two and more than two metal layers for underpass. Therefore, underpasses with two metal layers are promising for RFIC designs of the octagonal inductors in 90 nm CMOS technology.
곽호영,권혁민,권성규,장재형,이환희,이성재,고성용,이원묵,이희덕,Kwak, Ho-Young,Kwon, Hyuk-Min,Kwon, Sung-Kyu,Jang, Jae-Hyung,Lee, Hwan-Hee,Lee, Song-Jae,Go, Sung-Yong,Lee, Weon-Mook,Lee, Hi-Deok 한국전기전자재료학회 2011 전기전자재료학회논문지 Vol.24 No.12
In this paper, reliability of the two sandwiched MIM capacitors of $Al_2O_3-HfO_2-Al_2O_3$ (AHA) and $SiO_2-HfO_2-SiO_2$ (SHS) with hafnium-based dielectrics was analyzed using two kinds of voltage stress; DC and AC voltage stresses. Two MIM capacitors have high capacitance density (8.1 fF/${\mu}m^2$ and 5.2 fF/${\mu}m^2$) over the entire frequency range and low leakage current density of ~1 nA/$cm^2$ at room temperature and 1 V. The charge trapping in the dielectric shows that the relative variation of capacitance (${\Delta}C/C_0$) increases and the variation of voltage linearity (${\alpha}$/${\alpha}_0$) gradually decreases with stress-time under two types of voltage stress. It is also shown that DC voltage stress induced greater variation of capacitance density and voltage linearity than AC voltage stress.
Plasma Nitrided Oxide와 Thermally Nitrided Oxide를 적용한 NMOSFET의 Flicker Noise와 신뢰성에 대한 비교 분석
이환희,권혁민,권성규,장재형,곽호영,이성재,고성용,이원묵,이희덕,Lee, Hwan-Hee,Kwon, Hyuk-Min,Kwon, Sung-Kyu,Jang, Jae-Hyung,Kwak, Ho-Young,Lee, Song-Jae,Go, Sung-Yong,Lee, Weon-Mook,Lee, Hi-Deok 한국전기전자재료학회 2011 전기전자재료학회논문지 Vol.24 No.12
In this paper, flicker noise characteristic and channel hot carrier degradation of NMOSFETs with plasma nitrided oixde (PNO) and thermally nitrided oxide (TNO) are analyzed in depth. Compared with NMOSFET with TNO, flicker noise characteristic of NMOSFET with PNO is improved significantly because nitrogen density in PNO near the Si/$SiO_2$ interface is less than that in TNO. However, device degradation of NMOSFET with PNO by channel hot carrier stress is greater than that with TNO although PMOSFET with PNO showed greater immunity to NBTI degradation than that with TNO in previous study. Therefore, concurrent investigation of the reliability as well as low frequency noise characteristics of NMOSFET and PMOSFET is required for the development of high performance analog MOSFET technology.
RFIC 설계에 응용 가능한 90nm 공정 기반 인덕터의 Quality factor 및 Effective inductance 분석
장성용,신종관,권혁민,권성규,성승용,황선만,장재형,이가원,이희덕,Jang, Seong-Yong,Shin, Jong-Kwan,Kwon, Hyuk-Min,Kwon, Sung-Kyu,Sung, Seung-Yong,Hwang, Sun-Man,Jang, Jae-Hyung,Lee, Ga-Won,Lee, Hi-Deok 대한전자공학회 2013 전자공학회논문지 Vol.50 No.11
본 논문에서는 RFIC 설계에 응용 가능한 인덕터의 Quality factor 및 Effective inductance를 비교 분석하기 위해 Octagonal 인덕터를 90nm CMOS 공정을 이용하여 제작하였다. 내부반경을 설계변수로 갖는 인덕터의 경우 내부반경이 증가함에 따라 Quality factor가 감소하고 Effective inductance의 값이 증가하였다. 회전수를 설계변수로 갖는 인덕터의 경우 금속의 회전수가 증가함에 따라 Quality factor의 값이 감소하고 Effective inductance의 값이 증가하는 것을 확인하였다. 따라서 RFIC 회로 설계에 있어서 인덕터의 구조는 Q-factor 및 inductance 각각의 상대적 중요도에 따라 선택 되어져야 된다고 할 수 있다. In this paper, octagonal inductors for RFIC designs was fabricated with 90nm CMOS Technology to compare its quality factor and the effective inductance as functions of radius and number of turn. The quality factor decreases as the inner radius and the number of metal turned increase. However, the effective inductance increases with the increasing the inner radius and the number of metal turned. Therefore, the inductor structure should be decided according to the relative importance of Q-factor and inductance.
CMOS 기술을 기반으로 제작된 정합 특성이 우수한 BJT 구조
정의정(Yi-Jung Jung),권혁민(Hyuk-Min Kwon),권성규(Sung-Kyu Kwon),장재형(Jae-Hyung Jang),곽호영(Ho-Young Kwak),이희덕(Hi-Deok Lee) 大韓電子工學會 2012 電子工學會論文誌-SD (Semiconductor and devices) Vol.49 No.5
본 논문에서는 CMOS 기반의 BJT 제작에 있어서 일반적인 BJT 구조에 비해 정합특성이 우수한 새로운 BJT 구조를 제안하고, 특성을 비교 분석하였다. 새로운 정합 구조가 기존의 정합 구조에 비해 콜렉터 전류 밀도 Jc는 0.361% 감소하였고, 전류이득 β는 0.166% 증가하여 큰 차이가 보이지 않았지만, 소자 면적이 10% 감소했으며, 콜렉터 전류(AIc)와 전류이득(Aβ)의 정합 특성이 각각 45.74%, 38.73% 향상되었다. 이와 같이 정합특성이 개선된 주 이유는 쌍으로 형성된 BJT 소자들의 에미터 간의 거리가 감소한 것이라고 생각되며, deep n-well 저항의 표준편차 값이 다른 저항들에 비해 큰 것으로부터 간접적으로 증명이 된다고 여겨진다. For CMOS based bipolar junction transistor (BJT), a novel BJT structure which has higher matching property than conventional BJT structure was proposed and analyzed. The proposed structure shows a slight decrease of collector current density, JC about 0.361% and an increase of current gain, β about 0.166% compared with the conventional structure. However, the proposed structure shows a decrease of area about 10% the improvement of matching characteristics of collector current (AIC) and current gain (Aβ) about 45.74% and 38.73% respectively. The improved matching characteristic of proposed structure is believed to be mainly due to the decreased distance between two emitters of pair BJTs, which results in the decreased effect of deep n-well of which resistance has the higher standard deviation than the other resistances.