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Optimization of Silicon Quantum Dot Fabrication on Oxide and Nitride Films
Hyungcheol Shin,Jongho Lee 한국정보과학회 1999 Journal of Electrical Engineering and Information Vol.4 No.4
We have developed an LPCVD process of forming small-sized, high-density silicon quantum dots by investigating the effect of substrate type, chemical treatment, deposition temperature, and deposition time. Repeated results were obtained after several experiments under the same conditions when fabricating uniform quantum dots on Si₃N₄ and SiO₂ films. This ability to precisely control the size, density, and uniformity indicates the feasibility of practical nano-crystal non-volatile memory.
A Digital TCXO with New Trimming Method
Hyungcheol Shin,Min-Kyu Jeon,Kyungmi Lee 에스케이텔레콤 (주) 2000 Telecommunications Review Vol.10 No.6
Recently, the demand for the stable temperature compensated crystal oscillators (TCXO) is increasing more and more and digital TCXOs (DTCXO) have been studied extensively because of their higher frequency accuracy and onechip implementation possibility. To develop a VLSI TCXO circuit, the DTCXO using capacitor array which is directly controlled by the digital code from the memory was proposed and how to organize the capacitor array has been studied. In this work, a new capacitor array scheme, called TACA (temperature compensated capacitor array) is proposed. It guarantees monotonicity and saves the silicon area at the same time. We also have developed TCXO, which can be used over wide range of frequency. The oscillator and the capacitor array were fabricated with a 0.5μm CMOS process. Complete digital trimming of the DTCXO with 0.2ppm trimming accuracy was achieved.
Analytical Thermal Noise Model of Deep-submicron MOSFETs
Hyungcheol Shin,Seyoung Kim,Jongwook Jeon 대한전자공학회 2006 Journal of semiconductor technology and science Vol.6 No.3
This paper presents an analytical noise model for the drain thermal noise, the induced gate noise, and their correlation coefficient in deepsubmicron MOSFETs, which is valid in both linear region and saturation region. The impedance field method was used to calculate the external drain thermal noise current. The effect of channel length modulation was included in the analytical equation. The noise behavior of MOSFETs with decreasing channel length was successfully predicted from our model.
Kwangseok Han,Hyungcheol Shin,Kwyro Lee 한국물리학회 2004 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.44 No.1
In this work, a physics-based drain current thermal noise model for short-channel MOSFETs was derived. The proposed model takes into account the velocity-saturation effect explicitly and the carrier heating effect implicitly in the gradual channel region. A diffusion noise source was used to model the local noise generated in a segment of the inversion layer macroscopically, and the impedance field was recalculated when considering the velocity saturation effect. Finally, the proposed model suggests that the increase in the thermal noise for short-channel MOSFETs originates dominantly from the channel length modulation effect.
Design of a 20 nm T-Gate MOSFET with a Source/Drain-to-Gate Non-overlapped Structure
Hyunjin Lee,Hyungcheol Shin,이종호 한국물리학회 2004 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.44 No.1
A metal-oxide-semiconductor field-effect transistor (MOSFET) structure with a non-overlapped source-drain to T-gate is proposed to overcome the challenges in fabricating sub-30 nm complementary MOS (CMOS) devices. A high- spacer was adopted to induce eectively inversion layer in the non-overlapped region by using a fringing gate electric field, resulting in the suppression of the short-channel effects (SCEs). T-gate is used to reduce the gate resistance and to induce more carriers in the non-overlapped region to increase current drivability. The key device characteristics, including internal physics, were investigated by using extensive simulations. Compared to a conventional overlapped structure, the proposed structure has potential for the further scaling down.
Haechan Choi,Hyungcheol Shin 대한전자공학회 2023 대한전자공학회 학술대회 Vol.2023 No.6
We present a physical modeling for the transient program operation of barrier engineered charge-trapping NAND flash memory. Unlike existing models, we calculated the threshold voltage shift caused by each trapping layer by considering electron trapping in the ONO tunneling layer. We verified the rationality of our model through various parameter analyses.
Impact of Trap Position on Random Telegraph Noise in a 70-Å Nanowire Field-Effect Transistor
Lee, Hyunseul,Cho, Karam,Shin, Changhwan,Shin, Hyungcheol The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.2
A 70-${\AA}$ nanowire field-effect transistor (FET) for sub-10-nm CMOS technology is designed and simulated in order to investigate the impact of an oxide trap on random telegraph noise (RTN) in the device. It is observed that the drain current fluctuation (${\Delta}I_D/I_D$) increases up to a maximum of 78 % due to the single electron trapping. In addition, the effect of various trap positions on the RTN in the nanowire FET is thoroughly analyzed at various drain and gate voltages. As the drain voltage increases, the peak point for the ${\Delta}I_D/I_D$ shifts toward the source side. The distortion in the electron carrier density and the conduction band energy when the trap is filled with an electron at various positions in the device supports these results.
Yongmin Lee,Sungbak Kim,Hyungcheol Shin 대한전자공학회 2019 Journal of semiconductor technology and science Vol.19 No.6
In this paper, we analyzed and modeled the program disturbance caused by hot carrier injection(HCI) in 3D NAND flash memory. HCI in 3D NAND occurs by band-to-band tunneling(BTBT) due to large electric field near the programming cell in the inhibited string. The dependency of HCI on electric field was confirmed at various bias conditions. Also, HCI modeling was done by calculating the exact electric field considering the change of channel potential over time due to BTBT.