마이크로 산소분압센서용 Potentiostat 및 I-V Converter 회로 설계

서화일,최평,손병기 ( Hwa Il Seo,Pyung Choi,Byung Ki Sohn ) 한국센서학회 1994 센서학회지 Vol.3 No.3

Design of potentiostat and I-V converter for micro pO2 sensor is described. Also, The operation of the designed circuit, in connection with the eqivalent model of micro pO2 sensor, is simulated. The potentiostat showed low output resistance of 1.1㏀ and input voltage range of -3∼2.5V. And the I-V converter showed low input resistance of 30Ω and good linearity between input and output.

14 비트 분해능을 갖는 2차 Sigma-Delta 변조기 설계를 위한 구성요소의 최대에러 허용 범위 조사

조병욱,최평,손병기,Cho, Byung-Woog,Choi, Pyung,Sohn, Byung-Ki 한국통신학회 1998 韓國通信學會論文誌 Vol.23 No.5

저주파의 아날로그 신호를 디지털 신호로 변환하기 위해 sigma-delta 아날로그-디지털 변환기의 이용이 용이하다. 이 변환기는 변조기와 디지털 필터로 구성되는데 여기에서는 변조기에 대해 언급한다. 14비트 분해능을 갖는 2차 sigma-delta 변조기를 설계하기 위한 변조기의 구성요소 즉 연산 증폭기, 적분기, 내부 ADC 및 DAC의 최대 허용 에러 범위를 규정하였다. 이를 위하여 먼저 이상적인 변조기를 모델링하고 다음으로 변조기의 성능을 저하시키는 여러 가지 에러 요인 즉 연산증폭기의 최대 출력 제한, DC 이득, slew rate, 축전기의 불일치에 의한 적분기 이득 에러와 내부 ADC 및 DAC의 에러 등을 이상적인 모델에 적용하여 성능을 검증하였다. 이러한 에러 허용 범위에 대한 조사를 바탕으로 sigma-delta 변조기 설계 시 요구되는 구성 요소의 사양을 결정 할 수 있으며, 제조과정에서 나타나는 에러 성분에 대한 한계를 규정하여 최종 제작될 변조기의 성능을 확신 할 수 있다. Sigma-delta converter is frequently used for conyerting low-frequency anglog to digital signal. The converter consists of a modulator and a digital filer, but our work is concentrated on the modulator. In this works, to design second-order sigma-dalta modulator with 14bit resolution, we define maximumerror limits of each components (operational smplifier, integrator, internal ADC, and DAC) of modulator. It is first performed modeling of an ideal second-order sigma-delta modulator. This is then modified by adding the non-ideal factors such as limit of op-amp output swing, the finit DC gain of op-amp slew rate, the integrator gian error by the capacitor mismatch, the ADC error by the cmparator offset and the mismatch of resistor string, and the non-linear of DAC. From this modeling, as it is determined the specification of each devices requeired in design and the fabrication error limits, we can see the final performance of modulator.

14 비트 분해능을 갖는 2차 Sigma-Delta 변조기 설계 및 검증

조병욱,최평,손병기,Cho, Byung-Woog,Choi, Pyung,Sohn, Byung-Ki 대한전자공학회 1999 電子工學會論文誌, S Vol.s36 No.5

저주파의 아날로그 신호를 디지털 신호로 변환하기 위해 sigma-delta 아날로그-디지털 변환기의 이용이 용이하다. 이 변환기는 변조기와 디지털 필터로 구성되는데 본 논문에서는 변조기에 대해서만 언급한다. 모델링을 통해 14비트 분해능을 갖는 2차 sigma-delta 변조기를 설계하기 위한 변조기의 구성요소 즉 연산 증폭기, 적분기, 내부 ADC 및 DAC의 최대 허용 에러 범위를 규정하였으며, 이를 토대로 연산증폭기, 2비트 ADC 및 DAC 등을 설계·검증하고, 이들을 서로 연결하여 2차 sigma-delta 변조기를 구성하였다. 3비트 ADC의 기준전압을 조절하여 변조기 성능 향상을 도모하였으며, 내부 DAC를 축전기 및 간단한 제어회로로 구성하여 비선형성 에러를 최소화하였다. 설계된 각각의 구성요소들은 모델링에서 정의된 에러 범위를 모두 만족하였으며, 전체 변조기는87㏈의 입력범위와 87㏈의 최대 신호 대 잡음 비를 가졌다.

직접 궤환 방식의 모델링을 이용한 4차 시그마-델타 변환기의 설계

이범하,최평,최준림,Lee, Bum-Ha,Choi, Pyung,Choi, Jun-Rim 대한전자공학회 1998 電子工學會論文誌, C Vol.c35 No.6

본 논문에서는 오버샘플링 A/D변환기의 핵심 회로인 Σ-△변환기를 0.6㎛ CMOS공정을 이용하여 설계하였다. 설계과정은 우선 모델을 개발하여 S-영역에서 적절한 전달함수를 구한 후, 이를 시간 영역의 함수로 변환하여 연산 증폭기의 DC 전압이득, 슬루율과 같은 비 이상적인 요소들을 인가하여 검증하였다. 제안된 시그마-델타 변환기(Sigma-delta modulator, Σ-△변환기)는 음성 신호 대역에 대하여 64배 오버샘플링하며, 다이나믹 영역은 110 dB이상, 최대 S/N비는 102.6 dB로 설계하였다. 기존의 4차 Σ-△ 변환기는 잡음에 대한 전송영점의 위치를 3,4차 적분기단에 인가하는데 반하여 제안된 방식은 잡음에 대한 전송영점을 1,2차 적분기단에 인가함으로써 전체적인 커패시터의 크기가 감소하여 회로의 실질적인 면적이 감소하며, 성능이 개선되고, 소모 전력이 감소하였다. 또한 단위시간에 대한 출력값의 변화량이 3차 적분기의 경우에 비하여 작으므로 동작이 안정적이고, 1차 적분기의 적분 커패시터의 크기가 크므로 구현이 용이하며, 잡음에 대한 억제효과를 이용하여 3차 적분기단의 크기를 감소시켰다. 본 논문에서는 모델 상에서 전체적인 전달함수를 얻고, 신호의 차단주파수를 결정하며, 각 적분기의 출력신호를 최대화하여 적분기 출력신호의 크기를 증가시키고, 최대의 성능을 가지는 잡음에 대한 전송영점을 결정하는 기법을 제안한다. 설계된 회로의 실질적인 면적은 5.25 ㎟이고, 소모전력은 5 V 단일전원에 대하여 10 mW이다. A fourth-order $\Sigma$-$\Delta$ modulator is designed and implemented in 0.6 $\mu\textrm{m}$ CMOS technology. The modulator is verified by introducing nonlinear factors such as DC gain and slew rate in system model that determines the transfer function in S-domain and in time-domain. Dynamic range is more than 110 dB and the peak SM is 102.6 dB at a clock rate of 2.8224 MHz for voiceband signal. The structure of a ∑-$\Delta$ modulator is a modified fourth-order ∑-$\Delta$ modulator using direct feedback loop method, which improves performance and consumes less power. The transmission zero for noise is located in the first-second integrator loop, which reduces entire size of capacitors, reduces the active area of the chip, improves the performance, and reduces power dissipation. The system is stable because the output variation with respect to unit time is small compared with that of the third integrator. It is easy to implement because the size of the capacitor in the first integrator, and the size of the third integrator is small because we use the noise reduction technique. This paper represents a new design method by modeling that conceptually decides transfer function in S-domain and in Z-domain, determines the cutoff frequency of signal, maximizes signal power in each integrator, and decides optimal transmission-zero frequency for noise. The active area of the prototype chip is 5.25$\textrm{mm}^2$, and it dissipates 10 mW of power from a 5V supply.

고주파 발진형 근접 센서 시스템의 집적화를 위한 CMOS 회로 설계

성정우,최평 ( Jung Woo Sung,Pyung Choi ) 한국센서학회 1994 센서학회지 Vol.3 No.1

In the following paper, the high frequency oscillation proximity sensor system, one of the sensor systems used in FA, is designed using CMOS. According to the proximity of metal objects, two differing amplitudes of sinusoidal waves are set, and by using rectifiers, do voltages, which determine the constant current source circuit`s output current levels, can be abstracted from these waves. To remove any disturbances in the do voltage levels, a schmitt trigger is used. Some advantages of this CMOS high frequency oscillation proximity sensor are miniturization, light weight and low power disspation.

멀티센서신호 인터페이스용 Custom IC 를 위한 CMOS 회로 설계

조영창,최평,손병기 ( Young Chang Jo,Pyung Choi,Byung Ki Sohn ) 한국센서학회 1994 센서학회지 Vol.3 No.1

In this paper, the multi-sensor signal processing IC is designed. It consists of an analog multiplexer far selection of multi-sensor signals, active filters for noise rejection and signal amplification, and a sample and hold circuit for interface : with digital signal processing. By implementing these circuits with CMQS transistors, integration, low power dissipation and miniaturization of the total signal processing system have been made possible.

광통신 수신기용 클럭/데이타 복구회로 설계

이정봉,김성환,최평,Lee, Jung-Bong,Kim, Sung-Hwan,Choi, Pyung 대한전자공학회 1996 전자공학회논문지-A Vol.33 No.11

In the following paper, new architectural algorithm of clock and data recovery circuit is proposed for 622.08 Mbps optical communication receiver. New algorithm makes use of charge pump PLL using voltage controlled ring oscillator and extracts 8-channel 77.76 MHz clock signals, which are delayed by i/8 (i=1,2, ...8), to convert and recover 8-channel parallel data from 662.08 Mbps MRZ serial data. This circuit includes clock genration block to produce clock signals continuously even if input data doesn't exist. And synchronization of data and clock is doen by the method which compares 1/2 bit delayed onput data and decided dta by extracted clock signals. Thus, we can stabilize frequency and phase of clock signal even if input data is distorted or doesn't exist and simplify receiver architecture compared to traditional receiver's. Also it is possible ot realize clock extraction, data decision and conversion simulataneously. Verification of this algorithm is executed by DESIGN CENTER (version 6.1) using test models which are modelized by analog behavior modeling and digital circuit model, modified to process input frequency sufficiently, in SPICE.

CMOS 아날로그 집적회로를 위한 새로운 구조의 One port 저항 셀

조영창,김성환,최평,Jo, Young-Chang,Kim, Sung-Hwan,Choi, Pyung 대한전자공학회 1996 전자공학회논문지-A Vol.33 No.3

It is difficult to fabricate precise resistors for the analog integrated circuits using MOS technology. Until now polysilicon resistors were used at the analog integrated circuits, but some deviations of resistance and sensitive variation processes still cause their misactions. In order to improve these misactions, we suggest a CMOS resistor cell which provides precise resistance and excellant linearity. Also we designed the second order active low pass filter using the CMOS resistor cells and verified their superior performances compared to the actual resistors.

다채널 ISFET 측정용 단일 바이어스 회로의 설계

조병욱,김영진,김창수,최평,손병기 ( Byung Woog Cho,Young Jin Kim,Chang Soo Kim,Pyung Choi,Byung Ki Sohn ) 한국센서학회 1998 센서학회지 Vol.7 No.1

Multi-channel sensors can be used to increase the reliability and remove the random noise in ion-sensitive field effect transistors(ISFETs). Multi-channel sensors is also an essential step toward potential fabrication of sensors for several ionic species in one device. However, when the multi-channel sensors are separately biased, the biasing problems become difficult, that is to say, the bias circuit is needed as many sensors. In this work, a circuit for biasing the four pH-ISFETs in null-balance method, where bias voltages are switched, was proposed. The proposed concept is need only one bias circuit for the four sensors. Therefore it has advantages of smaller size and lower power consumption than the case that all sensors are separately biased at a time. The proposed circuit was tested with discrete devices and its performance was investigated. In the recent trend, sensor systems are implemented as portable systems. So the verified measurement circuit was integrated by using the CMOS circuit. Fortunately, ISFET fabrication process can be compatible with CMOS process. Full circuit has a mask area of 660㎛ x 500㎛. In the future, this step will be used for developing the smart sensor system with ISFET.

전송 게이트가 내장된 Gate/Body-Tied P-Channel Metal-Oxide Semiconductor Field-Effect Transistor 구조 광 검출기를 이용한 감도 가변형 능동 화소 센서

장준영 ( Juneyoung Jang ),이제원 ( Jewon Lee ),권현우 ( Hyeunwoo Kwen ),서상호 ( Sang-ho Seo ),최평 ( Pyung Choi ),신장규 ( Jang-kyoo Shin ) 한국센서학회 2021 센서학회지 Vol.30 No.2

In this study, the sensitivity of an active pixel sensor (APS) was adjusted by employing a gate/body-tied (GBT) p-channel metal-oxide semiconductor field-effect transistor (PMOSFET)-type photodetector with a transfer gate. A GBT PMOSFET-type photodetector can amplify the photocurrent generated by light. Consequently, APSs that incorporate GBT PMOSFET-type photodetectors are more sensitive than those APSs that are based on p-n junctions. In this study, a transfer gate was added to the conventional GBT PMOSFET-type photodetector. Such a photodetector can adjust the sensitivity of the APS by controlling the amount of charge transmitted from the drain to the floating diffusion node according to the voltage of the transfer gate. The results obtained from conducted simulations and measurements corroborate that, the sensitivity of an APS, which incorporates a GBT PMOSFET-type photodetector with a built-in transfer gate, can be adjusted according to the voltage of the transfer gate. Furthermore, the chip was fabricated by employing the standard 0.35 μm complementary metal-oxide semiconductor (CMOS) technology, and the variable sensitivity of the APS was thereby experimentally verified.