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Phase Error Accumulation Methodology for On-chip Cell Characterization
강창수,임인호,Kang, Chang-Soo,Im, In-Ho The Institute of Electronics and Information Engin 2011 電子工學會論文誌 IE (Industry electronics) Vol.37 No.3
본 논문은 나노 구조에서 ASIC 표준 라이브러리 셀의 특성에 대하여 전파지연시간 측정의 새로운 설계 방법을 제시하였다. 라이브러리 셀((NOR, AND, XOR 등)에 대한 정확한 시간 정보를 제공함으로서 ASIC 설계 흐름 공정의 시간적 분석을 증진시킬 수 있다. 이러한 분석은 기술 공정에서 반도체 파운드리 팀에게 유용하게 사용할 수 있다. CMOS 소자의 전파지연시간과 SPICE 시뮬레이션 은 트랜지스터 파라미터의 정확도를 예측할 수 있다. 위상오차 축적방법 물리적 실험은 반도체 제조공정($0.11{\mu}m$, GL130SB)으로 실현하였다. 표준 셀 라이브러리에서 전파지연시간은 $10^{-12}$초 단위까지 정확성을 측정할 수 있었다. VLSI STPE를 위한 솔루션은 배치, 시뮬레이션, 그리고 검증에 사용할 수 있다. This paper describes the design of new method of propagation delay measurement in micro and nanostructures during characterization of ASIC standard library cell. Providing more accuracy timing information about library cell (NOR, AND, XOR, etc.) to the design team we can improve a quality of timing analysis inside of ASIC design flow process. Also, this information could be very useful for semiconductor foundry team to make correction in technology process. By comparison of the propagation delay in the CMOS element and result of analog SPICE simulation, we can make assumptions about accuracy and quality of the transistor's parameters. Physical implementation of phase error accumulation method(PHEAM) can be easy integrated at the same chip as close as possible to the device under test(DUT). It was implemented as digital IP core for semiconductor manufacturing process($0.11{\mu}m$, GL130SB). Specialized method helps to observe the propagation time delay in one element of the standard-cell library with up-to picoseconds accuracy and less. Thus, the special useful solutions for VLSI schematic-to-parameters extraction (STPE), basic cell layout verification, design simulation and verification are announced.
(Ba,Ca)SiO<sub>3</sub> Glass Frit 첨가에 따른 NKN-BT 세라믹스의 유전 완화 특성
배선기,신혜경,이승환,임인호,Bae, Seon Gi,Shin, Hyeo-Kyung,Lee, Seung-Hwan,Im, In-Ho 한국전기전자재료학회 2014 전기전자재료학회논문지 Vol.27 No.6
We investigated dielectric relaxation properties of $0.95(Na_{0.5}K_{0.5})NbO_3-0.05BaTiO_3$ ceramics by addition (0~0.3 wt%) of $(Ba,Ca)SiO_3$ glass frit. All composition of $0.95(Na_{0.5}K_{0.5})NbO_3-0.05BaTiO_3$ added $(Ba,Ca)SiO_3$ glass frit showed the same crystallographic properties, coexistence of orthorhombic and tetragonal phase. By increasing addition of $(Ba,Ca)SiO_3$ glass frit, the Curie temperatures of $0.95(Na_{0.5}K_{0.5})NbO_3-0.05BaTiO_3$ ceramics were decreased, whereas maximum dielectric constants of $0.95(Na_{0.5}K_{0.5})NbO_3-0.05BaTiO_3$ ceramics were dramatically increased. Especially the deviations of Curie temperature $0.95(Na_{0.5}K_{0.5})NbO_3-0.05BaTiO_3$ ceramics were increased by increasing amount of $(Ba,Ca)SiO_3$ glass frit, and it indicated that $0.95(Na_{0.5}K_{0.5})NbO_3-0.05BaTiO_3$ ceramics added $(Ba,Ca)SiO_3$ glass frit have relaxor characteristics.
Phase Error Accumulation Methodology for On-chip Cell Characterization
강창수(Chang Soo Kang),임인호(In Ho Im) 대한전자공학회 2011 電子工學會論文誌 IE (Industry electronics) Vol.48 No.2
본 논문은 나노 구조에서 ASIC 표준 라이브러리 셀의 특성에 대하여 전파지연시간 측정의 새로운 설계 방법을 제시하였다. 라이브러리 셀((NOR, AND, XOR 등)에 대한 정확한 시간 정보를 제공함으로서 ASIC 설계 흐름 공정의 시간적 분석을 증진시킬 수 있다. 이러한 분석은 기술 공정에서 반도체 파운드리 팀에게 유용하게 사용할 수 있다. CMOS 소자의 전파지연시간과 SPICE 시뮬레이션 은 트랜지스터 파라미터의 정확도를 예측할 수 있다. 위상오차 축적방법 물리적 실험은 반도체 제조공정(0.11㎛, GL130SB)으로 실현하였다. 표준 셀 라이브러리에서 전파지연시간은 10<SUP>-12</SUP>초 단위까지 정확성을 측정할 수 있었다. VLSI STPE를 위한 솔루션은 배치, 시뮬레이션, 그리고 검증에 사용할 수 있다. This paper describes the design of new method of propagation delay measurement in micro and nanostructures during characterization of ASIC standard library cell. Providing more accuracy timing information about library cell (NOR, AND, XOR, etc.) to the design team we can improve a quality of timing analysis inside of ASIC design flow process. Also, this information could be very useful for semiconductor foundry team to make correction in technology process. By comparison of the propagation delay in the CMOS element and result of analog SPICE simulation, we can make assumptions about accuracy and quality of the transistor’s parameters. Physical implementation of phase error accumulation method(PHEAM) can be easy integrated at the same chip as close as possible to the device under test(DUT). It was implemented as digital IP core for semiconductor manufacturing process(0.11㎛, GL130SB). Specialized method helps to observe the propagation time delay in one element of the standard-cell library with up-to picoseconds accuracy and less. Thus, the special useful solutions for VLSI schematic-to-parameters extraction (STPE), basic cell layout verification, design simulation and verification are announced.
배선기,신혜경,이석진,임인호,Bae, Seon Gi,Shin, Hyea-Kyoung,Lee, Suk-Jin,Im, In-Ho 한국전기전자재료학회 2015 전기전자재료학회논문지 Vol.28 No.2
We investigated the dielectric relaxation properties $0.5Ba(Zr_{0.2}Ti_{0.8})O_3-0.5(Ba_{0.7}Ca_{0.3})TiO_3$ ceramics with CuO addition. With increasing CuO addition, the lattice parameter was increased by substitution of small amount $Cu^{2+}$ ion in B-site of $0.5Ba(Zr_{0.2}Ti_{0.8})O_3-0.5(Ba_{0.7}Ca_{0.3})TiO_3$ ceramics. Also the grain size and the maximum dielectric constant of $0.5Ba(Zr_{0.2}Ti_{0.8})O_3-0.5(Ba_{0.7}Ca_{0.3})TiO_3$ ceramics was decreased with increasing amounts of CuO addition. Moreover, the diffused phase transition properties (${\gamma}$) of $0.5Ba(Zr_{0.2}Ti_{0.8})O_3-0.5(Ba_{0.7}Ca_{0.3})TiO_3$ ceramics was increased by compositional fluctuation with increasing of CuO amount, changed from 1.45 at 1 wt% CuO addition to 1.94 at 7 wt% CuO addition.
저온소결 PMN-PZT 압전세라믹의 소성시간에 따른 미세구조 및 압전특성
류주현,이창배,이상호,백동수,정영호,임인호,Yoo, Ju-Hyun,Lee, Chang-Bae,Lee, Sang-Ho,Paik, Dong-Soo,Jeong, Yeong-Ho,Im, In-Ho 한국전기전자재료학회 2005 전기전자재료학회논문지 Vol.18 No.3
In this paper, in order to develop the low temperature sintering ceramics for multilayer piezoelectric transformer, PMN-PZT ceramics were manufactured with the variations of sintering times, and their microstructural, piezoelectric and dielectric properties were investigated. Li$_2$CO$_3$ and Bi$_2$O$_3$ were used as sintering aids and the specimens were sintered during 30, 60, 90, 120, 150, and 180 minutes, respectively. At the specimen sintered during 90 minute, mechanical quality factor(Qm), electro-mechanical coupling factor(kp) and dielectric constant were showed the optimum values of 2,356, 0.504 and 1,266, respectively.
CuO 첨가에 따른 0.5Ba(Zr0.2Ti0.8)O3-0.5(Ba0.7Ca0.3)TiO3 세라믹스의 유전 이완 특성
배선기 ( Seon Gi Bae ),신혜경 ( Hyea Kyoung Shin ),이석진 ( Suk Jin Jin Lee ),임인호 ( In Ho Im ) 한국전기전자재료학회 2015 전기전자재료 Vol.28 No.2
We investigated the dielectric relaxation properties 0.5Ba(Zr0.2Ti0.8)O3-0.5(Ba0.7Ca0.3)TiO3 ceramics with CuO addition. With increasing CuO addition, the lattice parameter was increased by substitution of small amount Cu2+ion in B-site of 0.5Ba(Zr0.2Ti0.8)O3-0.5(Ba0.7Ca0.3)TiO3 ceramics. Also the grain size and the maximum dielectric constant of 0.5Ba(Zr0.2Ti0.8)O3-0.5(Ba0.7Ca0.3)TiO3 ceramics was decreased with increasing amounts of CuO addition. Moreover, the diffused phase transition properties (γ) of 0.5Ba(Zr0.2Ti0.8)O3-0.5(Ba0.7Ca0.3)TiO3 ceramics was increased by compositional fluctuation with increasing of CuO amount, changed from 1.45 at 1 wt% CuO addition to 1.94 at 7 wt% CuO addition.