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Optimization of Reverse Engineering Processes for Cu Interconnected Devices
고진원,양준모,이형규,박근형 한국전기전자재료학회 2013 Transactions on Electrical and Electronic Material Vol.14 No.6
Reverse engineering of semiconductor devices utilizes delayering processes, in order to identify how the interconnection lines are stacked over transistor gates. Cu metal has been used in recent fabrication technologies,and de-processes becomes more difficult with the shrinking device dimensions. In this article, reverse engineering technologies to reveal the Cu interconnection lines and Cu via-plugs embedded in dielectric layers are investigated. Stacked dielectric layers are removed by CF4 plasma etching, then the exposed planar Cu metal lines and via-plugs are selectively delineated by wet chemical solution, instead of the commonly used plasma-based dry etch. As a result,we have been successful in extracting the layouts of multiple layers within a system IC, and this technique can be applicable to other logic IC, analog IC, and CMOS IC, etc.
고진원, 김성진, 이효원, 이형규 충북대학교 컴퓨터정보통신연구소 2012 컴퓨터정보통신연구 Vol.20 No.1
Rubrene thin TFT has shown higher hole mobility than other organics but further improvement is needed by poly-crystallization. We have attempted the grain growth during film deposition in vacuum by varying both of the substrate and source temperature, but no film deposition without poly-crystallization has occurred due to the higher re-evaporation rate from substrate than the deposition. Post-anneal at 170℃ on a hot plate has induced noticeable grain growth within 1 min utilizing a 20nm-thin film prepared at low temperature. Exposing excimer laser pulses or continuous UV lamp on the film has not brought any poly-crystallization but ablated the surface by excimer laser pulses with an optical power density of 50 cm2/V-s. keywords : Rubrene, Thermal anneal, Excimer laser anneal, Organic TFT
임태흥(Tae Heung Lim),왕성식(Sungsik Wang),고진원(Jinwon Ko),고민호(Minho Go),서철헌(ChulHun Seo),추호성(Hosung Choo) 대한전자공학회 2019 전자공학회논문지 Vol.56 No.1
본 논문에서는 AREPS(Advanced Refractive Effects Prediction System) 시뮬레이션을 사용하여 공대공 AESA 레이다 전파특성 및 표적 탐지를 위한 경로손실 값을 분석하였다. 국내 도심 지역의 지형 정보를 반영하고 실측 대기 특성을 기반으로 한 trilinear 수정 대기 굴절률을 모델링하여, normal, surface duct, elevated duct, combined atmospheric condition 대기에 대한 네 가지 시나리오를 설정하였다. 또한, zx-plane에서 4.4°의 HPBW와 35.7dB의 SLL을 가지는 AESA 레이다 배열안테나의 방사패턴을 적용하여 네 가지 시나리오에 따른 경로손실 값을 도출하였다. 고도 5000 m에 위치시킨 AESA 레이다를 전면 방향으로 조향 하였을 때, combined condition에서 150 km 거리의 경로 손실 값이 171 dB로 계산되어 전면방향으로 표적 탐지 성능이 저하되는 결과를 확인하였다. Combined atmospheric condition의 대기 상태에서 trap의 높이와 두께를 변화시키며 고도 5000 m의 전면방향 표적 위치에 대한 경로손실을 분석하였으며, trap이 발생한 높이 h2가 AESA 레이다 위치와 유사한 4800 m부터 5200 m까지 위치할 때 표적탐지 성능이 많이 열화되는 것을 확인하였다. In this paper, we analyzed the radar wave propagation characteristics for air-to-air AESA radars and calculated the path loss for estimating target detection performance using Advanced Refractive Effects Prediction System (AREPS) simulation software. Four atmospheric scenarios of normal, surface duct, elevated duct, and combined atmospheric conditions were set up by using the trilinear modified refractivity model, including the terrain data of the urban area of Korea. In addition, we applied the radiation pattern of the AESA radar array antenna with HPBW of 4.4° and SLL of 35.7 dB in zx-plane to the path loss simulations with four atmospheric scenarios. When AESA radar located at a height of 5000 m is steered to the bore-sight direction, the path loss of 171 dB is obtained at a distance of 150 km in the combined atmospheric condition, which indicates that the target detection performance in the bore-sight direction may be degraded. In the combined atmospheric condition, the path losses according to the variation of the trap height and thickness were obtained when the target was located at the height of 5000 m. It is found that the target detection performance is drastically deteriorated when the height h2 resides between 4800 m and 5200 m, where the trap height is similar to the AESA radar altitude.
이형규,김성진,강일석,이기성,김기남,고진원,Lee, Hyung Gyoo,Kim, Sung Jin,Kang, Il-Suk,Lee, Gi Sung,Kim, Ki Nam,Koh, Jin Won 한국전기전자재료학회 2016 전기전자재료학회논문지 Vol.29 No.3
Graphene has a monolayer crystal structure formed with C-atoms and has been used as a base layer of HETs (hot electron transistors). Graphene HETs have exhibited the operation at THz frequencies and higher current on/off ratio than that of Graphene FETs. In this article, we report on the preliminary results of current characteristics from the HETs which are fabricated utilizing highly doped Si collector, graphene base, and 5 nm thin $Al_2O_3$ tunnel layers between the base and Ti emitter. We have observed E-B forward currents are inherited to tunneling through $Al_2O_3$ layers, but have not noticed the Schottky barrier blocking effect on B-C forward current at the base/collector interface. At the common-emitter configuration, under a constant $V_{BE}$ between 0~1.2V, $I_C$ has increased linearly with $V_{CE}$ for $V_{CE}$ < $V_{BE}$ indicating the saturation region. As the $V_{CE}$ increases further, a plateau of $I_C$ vs. $V_{CE}$ has appeared slightly at $V_{CE}{\simeq}V_{BE}$, denoting forward-active region. With further increase of $V_{CE}$, $I_C$ has kept increasing probably due to tunneling through thin Schottky barrier between B/C. Thus the current on/off ration has exhibited to be 50. To improve hot electron effects, we propose the usage of low doped Si substrate, insertion of barrier layer between B/C, or substrates with low electron affinity.