1700 V급 EST소자의 설계 및 제작에 관한 연구

강이구,안병섭,남태진,Kang, Ey-Goo,Ahn, Byoung-Sub,Nam, Tae-Jin 한국전기전자재료학회 2010 전기전자재료학회논문지 Vol.23 No.3

In this paper, the trench gate emitter switched thyristor(EST) withl trench gate electrode is proposed for improving snap-back effect which leads to a lot of problems in device applications. The parasitic thyristor which is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The dual trench gate allows homogenous current distribution in the EST and preserves the unique feature of the gate controlled current saturation of the thyristor current. The characteristics of the 1700 V forward blocking EST obtained from two-dimensional numerical simulations (MEDICI) is described and compared with that of a conventional EST. we carried out layout, design and process of EST devices.

낮은 온저항과 칩 효율화를 위한 Unified Trench Gate Power MOSFET의 설계에 관한 연구

강이구,Kang, Ey-Goo 한국전기전자재료학회 2013 전기전자재료학회논문지 Vol.26 No.10

Power MOSFET operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. We have optimal designed planar and trench gate power MOSFET for high breakdown voltage and low on resistance. When we have designed $6,580{\mu}m{\times}5,680{\mu}m$ of chip size and 20 A current, on resistance of trench gate power MOSFET was low than planar gate power MOSFET. The on state voltage of trench gate power MOSFET was improved from 4.35 V to 3.7 V. At the same time, we have designed unified field limit ring for trench gate power MOFET. It is Junction Termination Edge type. As a result, we have obtained chip shrink effect and low on resistance because conventional field limit ring was convert to unify.

지능형 무선 센서네트워크 구현을 위한 USN/RFID 모듈의 설계 및 제작에 관한 연구

강이구,정헌석,이준환,현득창,황성일,송봉섭,이상훈,김영진,오상익,주숭호,이세창,Kang Ey Goo,Chung Hun-Suk,Lee Jun-Hwan,Hyun Deuk Chang,Hwang Sung-Il,Song Bong-Seob,Lee Sang-Hun,Kim Young-Jin,Oh Sang-Ik,Ju Seung-Ho,Lee Se-Chang 한국전기전자재료학회 2006 전기전자재료학회논문지 Vol.19 No.3

This paper was proposed Intelligent and wireless USN/RFID module system that can overcome disadvantage of existing RFID system with no sensing module and wire communication. The proposed USN/RFID system was designed and fabricated. After fabricating new system, we analyzed the characteristics of USN/RFID module. After design VCO block that is point circuit to develop next generation system one chip of RFID system, we were carried out simulation and verified the validity. this paper was showed that VCO system was enough usable in wireless network module. USN/RFID Reader module shows superior result that validity awareness distance corresponds to 30 M in the case of USN and to 5 M in RFID Reader's case and 900 MHz of commercial frequency does practical use enoughly in range of high frequency. The USN/RFID Reader module is considered to act big role to Ubiqitous industry offering computing surrounding of new concept that is intelligence type service and that was associated to real time location system(RTLS), environment improvement/supervision, national defense, traffic administration etc.

다양한 게이트 구조에 따른 IGBT 소자의 전기적 특성 비교 분석 연구

강이구,Kang, Ey Goo 한국전기전자재료학회 2016 전기전자재료학회논문지 Vol.29 No.11

This research was carried out experiments of variety IGBTs for industrial inverter and electric vehicle. The devices for this paper were planar gate IGBT, trench gate IGBT and dual gate IGBT and we designed using same design and process parameters. As a result of experiments, the electrical characteristics of planar gate IGBT were 1,459 V of breakdown voltage, 4.04 V of threshold voltage and 4.7 V of on-state voltage drop. And the electrical characteristics of trench gate IGBT were 1,473 V of breakdown voltage, 4.11 V of threshold voltage and 3.17 V of on-state voltage drop. Lastly, the electrical characteristics of dual gate IGBT were 1,467 V of breakdown voltage, 4.14 V of threshold voltage and 3.08V of on-state voltage drop. We almost knew that the trench gate IGBT was superior to dual gate IGBT in terms of breakdown voltage. On the other hand, the dual gate IGBT was better than the trench gate IGBT in terms of on state voltage drop.

Stacked Single Crystal Silicon TFT Cell의 적용에 의한 SRAM 셀의 전기적인 특성에 관한 연구

강이구,김진호,유장우,김창훈,성만영,Kang, Ey-Goo,Kim, Jin-Ho,Yu, Jang-Woo,Kim, Chang-Hun,Sung, Man-Young 한국전기전자재료학회 2006 전기전자재료학회논문지 Vol.19 No.4

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

플로팅 아일랜드 구조의 전력 MOSFET의 전기적 특성 분석

강이구,Kang, Ey Goo 한국전기전자재료학회 2016 전기전자재료학회논문지 Vol.29 No.4

This paper was proposed floating island power MOSFET for lowering on state resistance and the proposed device was maintained 600 V breakdown voltage. The electrical field distribution of floating island power MOSFET was dispersed to floating island between P-base and N-drift. Therefore, we designed higher doping concentration of drift region than doping concentration of planar type power MOSFET. And so we obtain the lower on resistance than on resistance of planar type power MOSFET. We needed the higher doping concentration of floating island than doping concentration of drift region and needed width and depth of floating island for formation of floating island region. We obtained the optimal parameters. The depth of floating island was $32{\mu}m$. The doping concentration of floating island was $5{\times}1,012cm^2$. And the width of floating island was $3{\mu}m$. As a result of designing the floating island power MOSFET, we obtained 723 V breakdown voltage and $0.108{\Omega}cm^2$ on resistance. When we compared to planar power MOSFET, the on resistance was lowered 24.5% than its of planar power MOSFET. The proposed device will be used to electrical vehicle and renewable industry.

GaN Power FET 모델링에 관한 연구

강이구,정헌석,김범준,이용훈,Kang, Ey-Goo,Chung, Hun-Suk,Kim, Beum-Jun,Lee, Young-Hun 한국전기전자재료학회 2009 전기전자재료학회논문지 Vol.22 No.12

In this paper, we proposed GaN trench Static Induction Transistor(SIT). Because The compound semiconductor had superior thermal characteristics, GaN and SiC power devices is next generation power semiconductor devices. We carried out modeling of GaN SIT with 2-D device and process simulator. As a result of modeling, we obtained 340 V breakdown voltage. The channel thickness was 3 urn and the channel doping concentration is $1e17\;cm^{-3}$. And we carried out thermal characteristics, too.

내압특성개선을 위한 트렌치 필드링 설계 및 전기적특성에 관한 연구

강이구,김범준,이용훈,Kang, Ey-Goo,Kim, Beum-Jun,Lee, Young-Hun 한국전기전자재료학회 2010 전기전자재료학회논문지 Vol.23 No.1

In this paper, we proposed trench field ring for breakdown voltage of power devices. The proposed trench field ring was improved 10% efficiency comparing with conventional field ring. we analyzed five parameters of trench field ring for design of trench field ring and carried out 2-D devices simulation and process simulations. That is, we analyzed number of field ring, juction depth, distance of field rings, trench width, doping profield. The proposed trench field ring was better to more 1000 V.

LED Driver ICs칩의 소형화를 위한 Chip on Chip 기술에 관한 연구

강이구,Kang, Ey Goo 한국전기전자재료학회 2016 전기전자재료학회논문지 Vol.29 No.3

This research was analyzed thermal characteristics that was appointed disadvantage when smart LED driver ICs was packaged and we applied extracted thermal characteristics for optimal layout design. We confirmed reliability of smart LED driver ICs package without additional heat sink. If the package is not heat sink, we are possible to minimize package. For extracting thermal loss due to overshoot current, we increased driver current by two and three times. As a result of experiment, we obtained 22 mW and 49.5 mW thermal loss. And we obtained optimal data of 350 mA driver current. It is important to distance between power MOSFET and driver ICs. If thhe distance was increased, the temperature of package was decreased. And so we obtained optimal data of 3.7 mm distance between power MOSFET and driver ICs. Finally, we fabricated real package and we analyzed the electrical characteristics. We obtained constant 35 V output voltage and 80% efficiency.

Super Junction MOSFET의 트렌치 식각 각도에 따른 열 특성 분석에 관한 연구

강이구,Kang, Ey Goo 한국전기전자학회 2014 전기전자학회논문지 Vol.18 No.4

본 논문에서는 Super Juction MOSFET의 우수한 열 특성을 검증하기 위해 도출된 공정 및 설계파라미터를 이용하여 열특성을 분석하였다. 열 특성 중 핵심공정인 Trench 식각 각도에 따른 온도차이, 열 저항, 그 때 흐르는 드레인 전류를 측정하여 전체 소비전력을 분석하였다. 분석한 결과 Trench 식각 각도가 $89.3^{\circ}$ 일 때 온도차와 열 저항 값이 가장 작게 나왔으며, 식각 각도에 따라서 분포는 경향성을 보이지 않았다. 따라서 반복 시뮬레이션과 실험을 통해 최적의 값을 도출해야 되며, 본 측정 결과 최적의 식각 각도는 $89.3^{\circ}$와 $89.6^{\circ}$의 결과를 보였다. 다른 전기적인 특성을 고려하여 최종 식각 각도를 보여야 하며, 열 특성의 우수한 SJ MOSFET이 산업에의 이용을 위해 본 논문의 자료가 충분히 활용할 수 있을 것으로 판단된다. This paper analyzed thermal characteristics of super junction MOSFET using process and design parameters. Trench process is very important to super junction MOSFET process. We analyzed the difference of temperature, thermal resistance, total power consumption according to trench etch angle. As a result we obtained minimum value of temperature difference and thermal resistance at $89.3^{\circ}$ of trench etch angle. The electrical characteristics distribution of super junction MOSFET is not showed tendency according to trench etch angle. We need iterative experiments and simulation for optimal value of electrical characteristics. The super junction power MOSFET that has superior thermal characteristics will use automobile and industry.