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Yang, Younghwi,Jeong, Hanwool,Song, Seung Chul,Wang, Joseph,Yeap, Geoffrey,Jung, Seong-Ook IEEE 2016 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.63 No.7
<P>Although near-threshold voltage (NTV) operation is an attractive means of achieving high energy efficiency, it can degrade the circuit stability of static random access memory (SRAM) cells. This paper proposes an NTV 7T SRAM cell in a 14 nm FinFET technology to eliminate read disturbance by disconnecting the path from the bit-line to the cross-coupled inverter pair using the transmission gate. In the proposed 7T SRAM cell, the half-select issue is resolved, meaning that no write-back operation is required. A folded-column structure is applied to the proposed 7T SRAM cell to reduce the read access time and energy consumption. To reduce the standby power, the proposed 7T SRAM cell uses only a single bit-line for both read and write operations. To achieve proper '1' writing operation with a single bit-line, a two-phase approach is proposed. Compared to the conventional 8T SRAM cell, the proposed 7T SRAM cell improves the read access time, energy, and standby power by 13%, 42%, and 23%, respectively, with a 3% smaller cell area.</P>
Younghwi Yang,Juhyun Park,Seung Chul Song,Wang, Joseph,Yeap, Geoffrey,Seong-Ook Jung IEEE 2015 IEEE transactions on very large scale integration Vol.23 No.11
<P>Although near-threshold (Vth) operation is an attractive method for energy and performance-constrained applications, it suffers from problems in terms of circuit stability, particularly, for static random access memory (SRAM) cells. This brief proposes a near-Vth 9T SRAM cell implemented in a 22-nm FinFET technology. The read buffer of the proposed cell ensures read stability by decoupling the stored node from the read bit-line and improves read performance using a one-transistor read path. Energy and standby power are reduced by eliminating the sub-Vth leakage current in the read buffer. For accurate sensing yield estimation, a new yield-estimation method is also proposed, which considers the dynamic trip voltage. The proposed SRAM cell can achieve a minimum operating voltage of 0.3 V.</P>
Younghwi Yang,Juhyun Park,Seung Chul Song,Wang, Joseph,Yeap, Geoffrey,Seong-Ook Jung IEEE 2015 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.62 No.6
<P>As the semiconductor technology scales down, the read stability and write ability of a static random-access memory (SRAM) cell are degraded because of the increased mismatch among its transistors. Extremely thin silicon-on-insulator is one of the attractive candidates to reduce this mismatch, and it offers an independent back-gate control using a thin buried oxide. The implementation of back-gate control has recently attracted much interest to improve the read stability and write ability. In this paper, we propose a selective cell current (ICELL) boosting scheme (SIB) and an asymmetric back-gate control write-assist (ABC-WA) circuit. SIB enhances the read performance by selectively boosting ICELL of the SRAM cells. ABC-WA enhances the write ability by forward biasing the NMOSs at one side, which improves the write ability with reduction in the dynamic power overhead and without requiring a voltage generator. The proposed SRAM design improves the read performance and energy by 38.6% and 24.9%, respectively.</P>
Design of a 22-nm FinFET-Based SRAM With Read Buffer for Near-Threshold Voltage Operation
Juhyun Park,Younghwi Yang,Hanwool Jeong,Seung Chul Song,Wang, Joseph,Yeap, Geoffrey,Seong-Ook Jung Institute of Electrical and Electronics Engineers 2015 IEEE transactions on electron devices Vol. No.
<P>A near-threshold voltage (V<SUB>th</SUB>) operation circuit is important for both energy- and performance-constrained applications. The conventional 6-T SRAM bit-cell designed for super-V<SUB>th</SUB> operation cannot achieve the target SRAM bit-cell margins such as the hold stability, read stability, and write ability margins in the near-V<SUB>th</SUB> region. The recently proposed SRAM bit-cells with read buffer suffer from the problems of low read 0 sensing margin and large read 1 sensing time in the near-V<SUB>th</SUB> region. This paper proposes a read buffer with adjusted the number of fins or V<SUB>th</SUB> to resolve the problems in the near-V<SUB>th</SUB> region. This paper also proposes a design method for pull-up, pull-down, and pass-gate transistors to achieve the target hold stability and presents an effective write assist circuit to achieve the target write ability in the near-V<SUB>th</SUB> region.</P>
Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM
Junyoung Ko,Younghwi Yang,Jisu Kim,Younghoon Oh,Park, H. K.,Seong-ook Jung IEEE 2017 IEEE transactions on circuits and systems. a publi Vol.64 No.6
<P>Research on phase-change random access memory (PRAM) for multilevel cells (MLCs) has been actively conducted owing to the advantages of PRAM cells, such as large resistance margin and fast read/write access time. However, the resistance drift (R-drift), which increases the resistance of the PRAM cells with time, should be overcome to achieve MLC PRAM operation. In this paper, we introduce sensing methods with R-drift tolerance, namely, drift-resilient cell-state metric and incremental bitline voltage (IBV), and compare these sensing methods in terms of the sensing margin and read access time. In addition, we propose a sensing scheme for IBV (IBVSS) with a half-adaptive threshold reference scheme (H-ATRS) to achieve high-R-drift tolerance in severe R-drift conditions with a small layout area for the reference cell. Verification of the IBVSS with H-ATRS is performed by HSPICE simulation using the 0.25-μm-model parameters used in the peripheral circuit of Samsung's 20-nm PRAM technology. From the simulation, we find that the IBVSS with H-ATRS achieves more than 1 V of sensing margin under severe R-drift conditions, which ensures stable read operation in the MLC PRAM with 304 ns of sensing time.</P>
Kyoman Kang,Hanwool Jeong,Younghwi Yang,Juhyun Park,Kiryong Kim,Seong-Ook Jung IEEE 2016 IEEE transactions on very large scale integration Vol.24 No.4
<P>The previously proposed average-8T static random access memory (SRAM) has a competitive area and does not require a write-back scheme. In the case of an average-8T SRAM architecture, a full-swing local bitline (BL) that is connected to the gate of the read buffer can be achieved with a boosted wordline (WL) voltage. However, in the case of an average-8T SRAM based on an advanced technology, such as a 22-nm FinFET technology, where the variation in threshold voltage is large, the boosted WL voltage cannot be used, because it degrades the read stability of the SRAM. Thus, a full-swing local BL cannot be achieved, and the gate of the read buffer cannot be driven by the full supply voltage (V-DD), resulting in a considerably large read delay. To overcome the above disadvantage, in this paper, a differential SRAM architecture with a full-swing local BL is proposed. In the proposed SRAM architecture, full swing of the local BL is ensured by the use of cross-coupled pMOSs, and the gate of the read buffer is driven by a full V-DD, without the need for the boosted WL voltage. Various configurations of the proposed SRAM architecture, which stores multiple bits, are analyzed in terms of the minimum operating voltage and area per bit. The proposed SRAM that stores four bits in one block can achieve a minimum voltage of 0.42 V and a read delay that is 62.6 times lesser than that of the average-8T SRAM based on the 22-nm FinFET technology.</P>
Hanwool Jeong,Taewon Kim,Younghwi Yang,Taejoong Song,Gyuhong Kim,Hyo-sig Won,Seong-Ook Jung IEEE 2015 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.62 No.4
<P>An offset-compensated cross-coupled PFET bit-line (BL) conditioning circuit (OC-CPBC) and a selective negative BL write-assist circuit (SNBL-WA) are proposed for high-density FinFET static RAM (SRAM). The word-line (WL) underdrive read-assist and the negative BL write-assist circuits should be used for the stable operation of high-density FinFET SRAM. However, the WL underdrive read-assist circuit degrades the performance, and the negative BL write-assist circuit consumes a large amount of energy. The OC-CPBC enhances BL development during the evaluation phase by applying cross-coupled PFETs whose offset is compensated by precharging each of the two BLs separately through diode-connected cross-coupled PFETs. The SNBL-WA performs a write assist only when a write failure is detected, and this selective write assist reduces the write energy consumption. The simulation results show that the performance and energy consumption are improved by 41% and 48%, respectively, by applying the OC-CPBC and SNBL-WA to SRAM, even with a decrease in area.</P>
SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis
Tae Hoon Choi,Hanwool Jeong,Younghwi Yang,Juhyun Park,Seong-Ook Jung IEEE 2017 IEEE transactions on circuits and systems. a publi Vol.64 No.8
<P>A static random access memory (SRAM) operational mismatch (SOMM) corner model and a methodology to efficiently estimate the SRAM read and write stability yield with the SOMM corner model are proposed. The proposed SOMM corner model effectively finds the combination of the transistor mismatch in SRAM, which represents the worst SRAM read or write operation in the given probabilistic distance (e.g., six sigma), and the SRAM yield can be estimated from the smallest probabilistic distance at which read or write operation failure occurs. With the proposed SOMM corner model implemented in the process design kit, the circuit designers can optimize the SRAM design by estimating the SRAM yield with significantly fewer computational resources, compared with the previous Monte Carlo-based methodologies. Numerical experiments show that the yield estimated by the proposed methodology matches well with the yield by Monte Carlo with importance sampling (error < 0.1 sigma); the simulation time takes less than 1 min, which is three orders of magnitude speedup over the conventional importance sampling methods.</P>
Power-Gated 9T SRAM Cell for Low-Energy Operation
Oh, Tae Woo,Jeong, Hanwool,Kang, Kyoman,Park, Juhyun,Yang, Younghwi,Jung, Seong-Ook Institute of Electrical and Electronics Engineers 2017 IEEE transactions on very large scale integration Vol.25 No.3
<P>This brief proposes a novel power-gated 9T (PG9T) static random access memory (SRAM) cell that uses a read-decoupled access buffer and power-gating transistors to execute reliable read and write operations. The proposed 9T SRAM cell uses bit interleaving to achieve soft error immunity and utilizes a column-based virtual V-SS signal to eliminate unnecessary bitline discharges in the unselected columns, thereby reducing the energy consumption. In a 22-nm FinFET technology, the proposed PG9T SRAM cell has a minimum operating voltage of 0.32 V while achieving the 6 sigma read stability yield. Compared with the previously proposed 9T SRAM cell, the proposed cell consumes 45% and 17% less energy per read and write operation, respectively, at the minimum operating voltage, and has a 12% smaller bit cell area.</P>