면외변위의 정량적 계측을 위한 ESPI와 Shearography의 비교

최정구,김경석,장호섭,정성욱 朝鮮大學校 機械技術硏究所 2005 機械技術硏究 Vol.8 No.2

Electronic Speckle Pattern Interfrometry is a common method for measuring out-of-plane displacement and in-plane displacement and applied for vibration analysis and strain/stress analysis. However, ESPI is sensitive to environmental disturbance, which provide the limitation of industrial application. On the other hand, Shearography based on shearing interferometer can directly measure the first derivative of out-of-plane displacement, which is insensitive to vibration disturbance. This paper proposes the out-of-plane displacement extraction technique from results of Shearography by numerical processing and measurement results of ESPI and Shearoraphy are compared quantitatively.

All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate

Jung, Dong-Hoon,Ryu, Kyungho,Park, Jung-Hyun,Jung, Seong-Ook IEEE 2018 IEEE transactions on very large scale integration Vol.26 No.6

<P>In this paper, an all-digital process-variation-calibrated high-performance timing generator for an automatic test equipment is proposed. The proposed timing generator generates process-variation-tolerant variable delays for high and wide-range testing clock frequency. In order to increase the testing clock frequency, a channel of the proposed timing generator consists of four subtiming generators operating in parallel. In addition, to improve process variation robustness, a precise eight-phase generator consisting of an accurate reference generator and a phase generator with dual-loop calibration (CAL) is proposed, and a phase error of less than 1.21° is achieved. Dynamic and static CAL techniques are also adopted in the edge vernier. A prototype chip having eight channels is fabricated using 0.13- <TEX>$\mu \text{m}$</TEX> CMOS technology. The proposed timing generator has an arbitrary test cycle frequency of up to 1.2 GHz, a timing resolution of 1.95 ps, a power consumption of 90 mW, and an area of 1.5 mm<SUP>2</SUP>.</P>

Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs

Jung-Hyun Park,Heechai Kang,Dong-Hoon Jung,Kyungho Ryu,Seong-Ook Jung IEEE 2015 IEEE transactions on very large scale integration Vol.23 No.3

<P>In this paper, we propose a level-converting retention flip-flop (RFF) for ZigBee systems-on-chips (SoCs). The proposed RFF allows the voltage regulator that generates the core supply voltage (VDD,core) to be turned off in the standby mode, and it thus reduces the standby power of the ZigBee SoCs. The logic states are retained in a slave latch composed of thick-oxide transistors using an I/O supply voltage (VDD,IO) that is always turned on. Level-up conversion from VDD,core to VDD,IO is achieved by an embedded nMOS pass-transistor level-conversion scheme that uses a low-only signal-transmitting technique. By embedding a retention latch and level-up converter into the data-to-output path of the proposed RFF, the RFF resolves the problems of the static RAM-based RFF, such as large dc current and low readability caused by threshold drop. The proposed RFF does not also require additional control signals for power mode transitioning. Using 0.13-μm process technology, we implemented an RFF with VDD,core and VDD,IO of 1.2 and 2.5 V, respectively. The maximum operating frequency is 300 MHz. The active energy of the RFF is 191.70 fJ, and its standby power is 350.25 pW.</P>

Race-Free Mixed Serial-Parallel Comparison for Low Power Content Addressable Memory

JUNG, Seong-Ook,YOON, Sei-Seung The Institute of Electronics, Information and Comm 2008 IEICE transactions on fundamentals of electronics, Vol.91 No.3

<P>This letter presents a race-free mixed serial-parallel comparison (RFMSPC) scheme which uses both serial and parallel CAMs in a match line. A self-reset search line scheme for the serial CAM is proposed to avoid the timing race problem and additional timing penalties. Various 32 entry CAMs are designed using 90nm 1.2V CMOS process to verify the proposed RFMSPC scheme. It shows that the RFMSPC saves power consumption by 40%, 53% and 63% at the cost of a 4%, 6% and 16% increase in search time according to 1, 2, and 4 serial CAM bits in a match line.</P>

ADDLL for Clock-Deskew Buffer in High-Performance SoCs

Jung-Hyun Park,Dong-Hoon Jung,Kyungho Ryu,Seong-Ook Jung IEEE 2013 IEEE transactions on very large scale integration Vol.21 No.7

<P>In this brief, we propose an all-digital delay locked loop (ADDLL) for a clock-deskew buffer. A low static phase offset at a high operating frequency is achieved by adopting a high-resolution window phase detector (PD) and a tristate-inverter-based ladder type coarse delay line (CDL). The proposed PD generates a high-resolution detection window that is adaptive to the process-voltage-temperature variation and reduces the static phase offset to nearly half of the fine delay line (FDL) resolution using a dual-output FDL. A proposed CDL is adopted in order to attain a small coarse delay step using tristate-inverters. The proposed ADDLL is designed using 0.13- μm process technology with a supply voltage of 1.2 V. The operating frequency range is 700 MHz to 2.0 GHz. The maximum static phase offset is less than 14.75 ps at all conditions and the power consumption is 4.0 mW at 2.0 GHz.</P>

<i>Sorbus commixta</i> water extract induces apoptotic cell death via a ROS-dependent pathway

Moon, Seong-Cheol,Choi, Hee-Jung,Chung, Tae-Wook,Lee, Jung-Hee,Lee, Syng-Ook,Jung, Myeong Ho,Kim, Byung Joo,Choi, Jun-Yong,Ha, Ki-Tae D.A. Spandidos 2018 Oncology letters Vol.16 No.4

<P>The stembark of <I>Sorbus commixta</I> Hedl. has been used for treating asthma, bronchitis, gastritis and edema. However, the anticancer and proapoptotic effects of the water extract of the stembark of <I>S. commixta</I> (SCE) remain unknown. In the present study, it was shown that SCE inhibited the cell viability of the hepatocellular carcinoma cell lines Hep3B and HepG2, and of the colon carcinoma cell line HCT116. DNA content analysis indicated that SCE increased the sub-G1 population of HCT116 cells. In addition, degradation of nuclear DNA and levels of proapoptotic cascade components, including caspase-9, caspase-3 and poly ADP-ribose polymerase, were augmented by SCE treatment. Mitochondrial membrane potential and the ratio of B-cell lymphoma-2 (Bcl-2)/Bcl-2-associated X protein (Bax) were also reduced. Furthermore, SCE increased the expression of proapoptotic proteins, including p21, p27 and p53. Mouse double minute 2 homology, a negative regulator of p53, was cleaved by SCE treatment. Intracellular reactive oxygen species (ROS) production was also increased by SCE treatment. However, the SCE-induced cytotoxic effects and the increased expression of proapoptotic proteins, including p53 and p21, and reduced Bcl-2/Bax ratio, could be attenuated by N-acetyl cysteine, an ROS inhibitor. Taken together, these results indicate that SCE is a potent proapoptotic herbal medicine, which exerts its effects via the ROS-mediated mitochondrial pathway.</P>

All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM

Dong-Hoon Jung,Young-Jae An,Kyungho Ryu,Jung-Hyun Park,Seong-Ook Jung IEEE 2015 IEEE Transactions on Circuits and Systems II: Expr Vol. No.

<P>A fast-locking all-digital delay-locked loop (DLL) with closed-loop duty-cycle correction (DCC) capability is proposed for clock synchronization in DRAM. A new cyclic-locking loop is proposed to resolve the locking speed degradation due to the replica delay line (RDL) in the DLL. The proposed cycliclocking loop operates asynchronously and offers an optimal loop delay for DLL locking. The locking time of the proposed DLL is decreased by more than 34.1% compared to that of previous fast-locking DLLs using a successive approximation register algorithm. The proposed DLL is fabricated using 65-nm CMOS process technology on an active area of 465.1 × 37 μm<SUP>2</SUP> and uses a 1.1-V supply voltage. The operating frequency range is 400-800 MHz, and 3.52 mW is consumed at 800 MHz, resulting in a power consumption of 4.4 pJ/Hz. The measured locking time ranges from 38 to 41 cycles over the entire operating frequency range.</P>

All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme

Dong-Hoon Jung,Kyungho Ryu,Jung-Hyun Park,Seong-Ook Jung IEEE 2016 IEEE transactions on very large scale integration Vol.24 No.3

<P>This paper proposes a 90 degrees phase-shift delay-locked loop (DLL) used in dynamic RAM for data sampling clock generation. The proposed DLL alleviates process variation issues, which are mainly caused by the mismatch between the delay line segments in the previous 90 degrees phase-shift DLLs, and reduces area by adopting a multiplying DLL-based structure. In addition, a novel jitter suppression scheme is also proposed to suppress control code dithering. A stochastic analysis is performed to evaluate the effectiveness of the proposed dithering jitter suppression. The proposed DLL is fabricated using a 45-nm CMOS process on an active area of 69.9 mu m x 49.3 mu m and utilizes a 1.1 V supply voltage. The proposed DLL has an operating frequency ranging from 500 to 800 MHz and consumes 1.32 mW at 800 MHz. The measured rms and peak-to-peak output jitters are improved by 5.42% to 18.75% and 5.52% to 18.31%, respectively, in the entire operating frequency range.</P>

Empirical Channel Model for Human Body Communication

Jung Hwan Hwang,Tae Wook Kang,Seong Ook Park,Youn Tae Kim IEEE 2015 IEEE antennas and wireless propagation letters Vol.14 No.-

<P>In this letter, an empirical channel model for human body communication (HBC) is presented based upon impulse response. For a channel model over a wide range of frequencies between 5 and 80 MHz, the amplitude of an impulse response is modeled with a random variable at each sampling point; the random variable is found using empirically obtained impulse responses with respect to multiple subjects of 70 human subjects. This empirical channel model is obtained when a signal transmitter and receiver are located on opposite hands. However, it provides a practical way to estimate the performance of HBC systems within an environment of multiple users and various devices.</P>

Measurement of Transmission Properties of HBC Channel and Its Impulse Response Model

Jung-Hwan Hwang,Tae-Wook Kang,Youn-Tae Kim,Seong-Ook Park Institute of Electrical and Electronics Engineers 2016 IEEE transactions on instrumentation and measureme Vol.65 No.1

<P>In human body communication (HBC), the human body is used as a medium for transmitting data between devices in order to replace wired and wireless technologies. This paper presents the measurement results on the transmission properties of an HBC channel and an impulse response model for the HBC channel. The HBC channel was measured with respect to multiple subjects, and the channel parameters were then obtained to analyze the subject dependency of the HBC channel. The HBC channel was modeled using impulse responses that were obtained from the measured channels. The measurement results and the impulse response model can be effectively used to estimate the performance of HBC devices, which is significantly influenced by an HBC channel.</P>