<P>As the semiconductor technology scales down, the read stability and write ability of a static random-access memory (SRAM) cell are degraded because of the increased mismatch among its transistors. Extremely thin silicon-on-insulator is one of...
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https://www.riss.kr/link?id=A107478890
2015
-
SCI,SCIE,SCOPUS
학술저널
1538-1545(8쪽)
0
상세조회0
다운로드다국어 초록 (Multilingual Abstract)
<P>As the semiconductor technology scales down, the read stability and write ability of a static random-access memory (SRAM) cell are degraded because of the increased mismatch among its transistors. Extremely thin silicon-on-insulator is one of...
<P>As the semiconductor technology scales down, the read stability and write ability of a static random-access memory (SRAM) cell are degraded because of the increased mismatch among its transistors. Extremely thin silicon-on-insulator is one of the attractive candidates to reduce this mismatch, and it offers an independent back-gate control using a thin buried oxide. The implementation of back-gate control has recently attracted much interest to improve the read stability and write ability. In this paper, we propose a selective cell current (ICELL) boosting scheme (SIB) and an asymmetric back-gate control write-assist (ABC-WA) circuit. SIB enhances the read performance by selectively boosting ICELL of the SRAM cells. ABC-WA enhances the write ability by forward biasing the NMOSs at one side, which improves the write ability with reduction in the dynamic power overhead and without requiring a voltage generator. The proposed SRAM design improves the read performance and energy by 38.6% and 24.9%, respectively.</P>
Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM