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HPr antagonizes the anti-σ<sup>70</sup> activity of Rsd in <i>Escherichia coli</i>
Park, Young-Ha,Lee, Chang-Ro,Choe, Mangyu,Seok, Yeong-Jae National Academy of Sciences 2013 PROCEEDINGS OF THE NATIONAL ACADEMY OF SCIENCES OF Vol.110 No.52
<P>The bacterial phosphoenolpyruvate:sugar phosphotransferase system (PTS) is a multicomponent system that participates in a variety of physiological processes in addition to the phosphorylation-coupled transport of numerous sugars. In <I>Escherichia coli</I> and other enteric bacteria, enzyme IIA<SUP>Glc</SUP> (EIIA<SUP>Glc</SUP>) is known as the central processing unit of carbon metabolism and plays multiple roles, including regulation of adenylyl cyclase, the fermentation/respiration switch protein FrsA, glycerol kinase, and several non-PTS transporters, whereas the only known regulatory role of the <I>E. coli</I> histidine-containing phosphocarrier protein HPr is in the activation of glycogen phosphorylase. Because HPr is known to be more abundant than EIIA<SUP>Glc</SUP> in enteric bacteria, we assumed that there might be more regulatory mechanisms connected with HPr. The ligand fishing experiment in this study identified Rsd, an anti-sigma factor known to complex with σ<SUP>70</SUP> in stationary-phase cells, as an HPr-binding protein in <I>E. coli</I>. Only the dephosphorylated form of HPr formed a tight complex with Rsd and thereby inhibited complex formation between Rsd and σ<SUP>70</SUP>. Dephosphorylated HPr, but not phosphorylated HPr, antagonized the inhibitory effect of Rsd on σ<SUP>70</SUP>-dependent transcriptions both in vivo and in vitro, and also influenced the competition between σ<SUP>70</SUP> and σ<SUP>S</SUP> for core RNA polymerase in the presence of Rsd. Based on these data, we propose that the anti-σ<SUP>70</SUP> activity of Rsd is regulated by the phosphorylation state-dependent interaction of HPr with Rsd.</P>
하창훈,권보준,이만규,Ha, Changhun,Kwon, Bojun,Lee, Mangyu 한국군사과학기술학회 2017 한국군사과학기술학회지 Vol.20 No.4
The radar signal processing procedure is divided into the pre-processing such as frequency down converting, down sampling, pulse compression, and etc, and the post-processing such as doppler filtering, extracting target information, detecting, tracking, and etc. The former is generally designed using FPGA because the procedure is relatively simple even though there are large amounts of ADC data to organize very quickly. On the other hand, in general, the latter is parallel processed by multiple DSPs because of complexity, flexibility and real-time processing. This paper presents the radar signal processor design using FPGA which includes not only the pre-processing but also the post-processing such as doppler filtering, bore-sight error, NCI(Non-Coherent Integration), CFAR(Constant False Alarm Rate) and etc.