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하창훈,권보준,이만규,Ha, Changhun,Kwon, Bojun,Lee, Mangyu 한국군사과학기술학회 2017 한국군사과학기술학회지 Vol.20 No.4
The radar signal processing procedure is divided into the pre-processing such as frequency down converting, down sampling, pulse compression, and etc, and the post-processing such as doppler filtering, extracting target information, detecting, tracking, and etc. The former is generally designed using FPGA because the procedure is relatively simple even though there are large amounts of ADC data to organize very quickly. On the other hand, in general, the latter is parallel processed by multiple DSPs because of complexity, flexibility and real-time processing. This paper presents the radar signal processor design using FPGA which includes not only the pre-processing but also the post-processing such as doppler filtering, bore-sight error, NCI(Non-Coherent Integration), CFAR(Constant False Alarm Rate) and etc.