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이효찬,문대철,박인학,허강,Lee, Hyo-Chan,Moon, Dai-Tchul,Park, In-hag,Heo, Kang 한국정보통신학회 2016 한국정보통신학회논문지 Vol.20 No.9
본 논문에서는 차선 검출 알고리즘에 병렬처리를 적용하여 성능을 개선하였다. 차선 검출은 지능형 보조 시스템으로써 자동차가 차선을 이탈하면 경보음 또는 핸들을 보정해줌으로써 운전자를 돕는 보조 시스템이다. 병렬 처리 알고리즘 중 데이터 레벨 병렬처리는 설계가 간단하지만 병목현상이 발생하는 문제가 있다. 제안하는 고속 데이터 레벨 병렬처리 알고리즘은 병목현상을 줄여 성능이 향상되었다. 실제 블랙박스 도로 영상을 도입하여 알고리즘을 측정한 결과 싱글 코어 경우 약 30 Frames/sec의 성능을 얻었다. 병렬처리를 적용한 결과로써 옥타코어 기준으로 데이터 레벨인 경우 약 100 Frames/sec의 성능을, 고속 데이터 레벨인 경우는 약 150 Frames/sec의 성능을 얻을 수 있다. we improved the performance by parallelizing lane detection algorithms. Lane detection, as a intellectual assisting system, helps drivers make an alarm sound or revise the handle in response of lane departure. Four kinds of algorithms are implemented in order as following, Gaussian filtering algorithm so as to remove the interferences, gray conversion algorithm to simplify images, sobel edge detection algorithm to find out the regions of lanes, and hough transform algorithm to detect straight lines. Among parallelized methods, the data level parallelism algorithm is easy to design, yet still problem with the bottleneck. The high-speed data level parallelism is suggested to reduce this bottleneck, which resulted in noticeable performance improvement. In the result of applying actual road video of black-box on our parallel algorithm, the measurement, in the case of single-core, is approximately 30 Frames/sec. Furthermore, in the case of octa-core parallelism, the data level performance is approximately 100 Frames/sec and the highest performance comes close to 150 Frames/sec.
Switched Gacitor 저역통과 여파기의 최적 설계에 관한 연구
許康仁 동아대학교 공과대학 부설 한국자원개발연구소 1983 硏究報告 Vol.7 No.2
In this paper, General techniques for realizing differential integrator transformation and reduced OP-Amp transformation in low pass SCF are presented. The results of experiment are as follows. 1. The realization of SCF by two transformation can be made satisfactorily. 2. Differents between theoretical values and measured ones are considered due to the tolerances of components. 3. The realization of SCF by reduced OP-Amp transformation has less than error than by conventional differential transformation. 4. It is concluded that error can be reduced siginificantly when we make these filters of MOS IC which has better temperature and linear characteristics.
디지탈 시스템에서의 Sampling-Rate 변환을 위한 FIR구조의 구성에 관한 연구
金明起,許康仁 동아대학교 공과대학 부설 한국자원개발연구소 1986 硏究報告 Vol.10 No.1
In this paper, A general theory of multistage Interpolator and decimator for sampling rate reduction and sampling rate increase is presented. The use of classical interpolation methods in signal processing application is illustrated by a discussion of FIR interpolation filters derived from the Lagrange interpolation formula. Example is presented to compute the unit sample response of a sampling rate converter which converts data from a sampling rate of M to L.
PCM Voice CODEC의 Switched Capacitor Filter의 구성에 관한 연구
변건식,허강인 동아대학교 공과대학 부설 한국자원개발연구소 1984 硏究報告 Vol.8 No.2
Three Switched Capacitor decimation and interpolation circuits are described which perform all filtering functions in PCM Voice CODEC. The decimator can function as an input stage, the interpolator as an output stage in a filter system. The CODEC consists of 2 chips- the transmit chip includes the companding coder along with filtering functions, and the receive chip consists of the expanding decoder chip with its smoothing filter. Experimental results show the circuit to meet accepted requirements.