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A method on the implementation of FIR(Finite Impulse Response) digital filter using stored square ROM multiplier is proposed. This paper describes that ROM requirement can be reduced by using the absolute value circuit and split address technique, and also execution speed can be improved by using the pipelining technique for stored square ROM multiplier. The frequency response of FIR digital filter simulated and implemented by the above method is quite agreeable with theoretical results computed by Remez exchange algorithm. All results stated assume the use of fixed point parallel arithmetic.
A method on the hardware implementation of the Finite Impulse Response (FIR) digital filter using Digital Quarter Square Multiphcation (DQSM) algorithm is proposed. ROM requirement can be reduced by using the double precision algorithm and the absolute value circuit, and also execution speed can be improved by reducing logic level steps of absolute value circuit. The frequency response of FIR digital filter implemented by the above method is quite agreeable with the frequency response simulated by Remez exchange algorithm. If coefficients should be stored in the RAM instead of the ROM, this method is especially useful in the case of FIR digital filter with time varying coefficients.
This paper examinated the fundamental investigation about transmission characteristics of parallel pair line. And we confirmed that spread spectrum communication system was very effective system in communication suing power line loss was located in particular frequency. As a result of experiment, it established its resonableness.
In this paper, A general theory of multistage Interpolator and decimator for sampling rate reduction and sampling rate increase is presented. The use of classical interpolation methods in signal processing application is illustrated by a discussion of FIR interpolation filters derived from the Lagrange interpolation formula. Example is presented to compute the unit sample response of a sampling rate converter which converts data from a sampling rate of M to L.
This paper proposes an approach to the approximate realization of two-dimensional FIR digital filters by using the decomposition of their coefficient matrices. This approach is based on the design method of multistage separable planar filters, and reduces with very small error the number of required computations(number of multiplications/additions), register coefficients and memories applying the intimate relationship between the eigen values of every stage and ranks of the matrices.
In implementing a digital filter with fixed-point arithemetic, additions may cause overflows to occur. In order to avoid overflows, the input signal may be attenuated suitably so that no overflows occur at any point in the filter. But this results in a low output signal-to-noise ratio. Lp Norm is the theoretical basis for scaling the signal level at different node in a digital filter to avoid overflows. The purpose of this paper is to describe a systematic procedure for scaling wave digital filter to avoid overflow problems while maintaining a signal-to-noise ratio as large as possible. The scaled WDF have an improved signal-to-noise ratio over unscaled WDF without overflow.