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저온 공정 PVP게이트 절연체를 이용한 고성능 플렉서블 유기박막 트랜지스터의 계면처리 효과
윤호진,백규하,신홍식,이가원,이희덕,도이미,Yun, Ho-Jin,Baek, Kyu-Ha,Shin, Hong-Sik,Lee, Ga-Won,Lee, Hi-Deok,Do, Lee-Mi 한국전기전자재료학회 2011 전기전자재료학회논문지 Vol.24 No.1
In this study, we fabricated the flexible pentacene TFTs with the polymer gate dielectric and contact printing method by using the silver nano particle ink as a source/drain material on plastic substrate. In this experiment, to lower the cross-linking temperature of the PVP gate dielectric, UV-Ozone treatment has been used and the process temperature is lowered to $90^{\circ}C$ and the surface is optimized by various treatment to improve device characteristics. We tried various surface treatments; $O_2$ Plasma, hexamethyl-disilazane (HMDS) and octadecyltrichlorosilane (OTS) treatment methods of gate dielectric/semiconductor interface, which reduces trap states such as -OH group and grain boundary in order to improve the OTFTs properties. The optimized OTFT shows the device performance with field effect mobility, on/off current ratio, and the sub-threshold slope were extracted as $0.63cm^2 V^{-1}s^{-1}$, $1.7{\times}10^{-6}$, and of 0.75 V/decade, respectively.
C54-TiSi2/SiO2 의 열적 불안정성에 미치는 계면 구조의 영향
백규하,서동우,김홍승,강진영 대한금속재료학회(대한금속학회) 2000 대한금속·재료학회지 Vol.38 No.8
C54-TiSi₂ grown on SiO₂ as an interconnect showed thermal instability, even skinning, through the rapid thermal anneal(RTA). In order to understand the thermal instability of C54-TiSi₂ the interface between the thin film and the substrate was analyzed with Auger electron spectroscopy(AES) and transmission electron microscopy(TEM). Also we quantitatively analysed residual stress using known thermal properties of C54-TiSi₂. It was noted, as a result, that considerable amounts of residual stress were released by silicon retained at the interface. Therefore surplus silicon should be prepared between titanium and substrate in order to make C54-TiSi₂ thermally stable, so that the surplus silicon may play a role of buffer against residual stress.