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기안도,Ki, An-do 한국전자통신연구원 1998 전자통신동향분석 Vol.13 No.4
The terminology of data prefetching is introduced, which includes stride, repeat distance, stall, pending stall, prefetch degree, prefetch distance, and prefetch offset. The effectiveness of hardware data prefetching in reducing cache misses is shown by presenting a square matrix multiplication example. Thereafter the pitfalls of prefetching and possible solutions are discussed.
기안도,Ki, An-Do 한국전자통신연구원 1998 전자통신동향분석 Vol.13 No.3
The obvious way to make a computer system more powerful is to make the processor as fast as possible. Furthermore, adopting a large number of such fast processors would be the next step. This multiprocessor system could be useful only if it distributes workload uniformly and if its processors are fully utilized. To achieve a higher processor utilization, memory access latency must be reduced as much as possible and even more the remaining latency must be hidden. The actual latency can be reduced by using fast logic and the effective latency can be reduced by using cache. This article discusses what the memory latency problem is, how serious it is by presenting analytical and simulation results, and existing techniques for coping with it; such as write-buffer, relaxed consistency model, multi-threading, data locality optimization, data forwarding, and data prefetching.
엄현선,최진영,한우종,기안도,심규현,Um, Hyun-Sun,Choi, JIn-Young,Han, Woo-Jong,Ki, An-Do,Shim, Kyu-Hyun 한국정보처리학회 2000 정보처리논문지 Vol.7 No.7
다중 프로세서 시스템에서 각각의 프로세서에 할당되어 있는 지역 캐쉬에 데이터의 복사본이 분산 공유되어 있는 경우 데이터의 일관성 유지가 필요하다. 따라서 캐쉬 일관성 유지 프로토코콜은 공유 메모리 다중 프로세서 시스템의 정확하고 효율적인 작동이 중요하다. 그러므로 시스템이 복잡해짐과 비례하여 현재 사용되고있는 무작위적 테스트나 시뮬레이션은 프로토콜의 정확성을 확인하기에 충분하지 못하므로 보다 효율적이고 믿을 만한 검증 방법이 필요하다. 본 논문은 ETRI에서 개발된 캐쉬 일관성 프로토콜인 RACE(Remote Access Cache coherent Enforcement)프로토콜의 몇 가지 특성(property)들을 정형기법에 쓰이는 도구 중이 하나인 VIS(Verification Interacting with Synthesis)를 이용하여 검증한다. Caches in a multiprocessing environment introduce the cache coherence problem. When multiple processors maintain locally cached copies of a unique shared-memory location, any local modification of the location can result in a globally inconsistent view of memory. Cache coherence protocols are important to operate a shared-memory multiprocessor system with efficiency and correctness. Since random testing and simulations are not enough to validate correctness of protocols, it is necessary to develop efficient and reliable verification methods. In this appear we present our experience in using VIS (Verification Interacting with Synthesis), a tool of formal method, to analyze a number of property of a cache coherence protocol, RACE (Remote Access Cache coherent Enforcement).
남원홍(Won-Hong Nam),성창훈(Chang-Hun Sung),최진영(Jin-Young Choi),기안도(An-Do Ki),한우종(Woo-Jong Han) 한국정보과학회 2000 한국정보과학회 학술발표논문집 Vol.27 No.1A
본 연구는 심볼릭 모델 체커 중의 하나인 SMV(Symbolic Model Verifier)를 이용하여 한국전자통신연구원(ETRI)에서 개발한 CCA (Cache Coherent Agent) 보드를 위한 I-Link Bus(Inside Bus)의 몇 가지 특성(property)들을 검증하여 I-Link Bus의 요구사항(requirement)이 만족됨을 보인다. 이 검증에서는 I-Link Bus의 모델을 SMV 입력 언어로 명세하며, 검증할 특성들을 시제 논리(temporal logic)를 이용하여 나타낸다. 검증을 통해서 I-Link Bus와 PIF(Processor Interface), DC(Directory Controller), RC(Remote access cache Controller) 모듈들이 중재기 우선 순위, send 우선 순위, 중재 요청 신호의 관리, liveness 등의 특성들을 만족한다라는 것을 검증하였다.
엄현선(Hyun Sun Um),최진영(Jin Young Choi),한우종(Woo Jong Han),기안도(An Do Ki),심규현(Kyu Hyun Shim) 한국정보처리학회 2000 정보처리학회논문지 Vol.7 No.7
Caches in a multiprocessing environment introduce the cache coherence problem. When multiple processors maintain locally cached copies of a unique shared-memory location, any local modification of the location can result in a globally inconsistent view of memory. Cache coherence protocols are important to operate a shared-memory multiprocessor system with efficiency and correctness. Since random testing and simulations are not enough to validate correctness of protocols, it is necessary to develop efficient and reliable verification methods. In this paper we present our experience in using VIS (Verification Interacting with Synthesis), a tool of formal method, to analyze a number of property of a cache coherence protocol, RACE (Remote Access Cache coherent Enforcement).