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엄현선,최진영,한우종,기안도,심규현,Um, Hyun-Sun,Choi, JIn-Young,Han, Woo-Jong,Ki, An-Do,Shim, Kyu-Hyun 한국정보처리학회 2000 정보처리논문지 Vol.7 No.7
다중 프로세서 시스템에서 각각의 프로세서에 할당되어 있는 지역 캐쉬에 데이터의 복사본이 분산 공유되어 있는 경우 데이터의 일관성 유지가 필요하다. 따라서 캐쉬 일관성 유지 프로토코콜은 공유 메모리 다중 프로세서 시스템의 정확하고 효율적인 작동이 중요하다. 그러므로 시스템이 복잡해짐과 비례하여 현재 사용되고있는 무작위적 테스트나 시뮬레이션은 프로토콜의 정확성을 확인하기에 충분하지 못하므로 보다 효율적이고 믿을 만한 검증 방법이 필요하다. 본 논문은 ETRI에서 개발된 캐쉬 일관성 프로토콜인 RACE(Remote Access Cache coherent Enforcement)프로토콜의 몇 가지 특성(property)들을 정형기법에 쓰이는 도구 중이 하나인 VIS(Verification Interacting with Synthesis)를 이용하여 검증한다. Caches in a multiprocessing environment introduce the cache coherence problem. When multiple processors maintain locally cached copies of a unique shared-memory location, any local modification of the location can result in a globally inconsistent view of memory. Cache coherence protocols are important to operate a shared-memory multiprocessor system with efficiency and correctness. Since random testing and simulations are not enough to validate correctness of protocols, it is necessary to develop efficient and reliable verification methods. In this appear we present our experience in using VIS (Verification Interacting with Synthesis), a tool of formal method, to analyze a number of property of a cache coherence protocol, RACE (Remote Access Cache coherent Enforcement).
Characteistics of a CMOS Differential Input-Stage Using a Source-Coupled Backgate Pair
강욱,이원형,한우종,김수원,Kang, Wook,Lee, Won-Hyeong,Han, Woo-Jong,Kim, Soo-Won The Institute of Electronics and Information Engin 1991 전자공학회논문지-A Vol.28 No.1
It is well known that the conventional differential source-coupled pair uses gates as its input terminals. This input pair provids a high open-loop gain, a large CMRR, and a good PSRR. For these reasons, the input pair has been used widely as an input stages of the differential amplifiers, but a narrow linear input range of this structurelimits its application in the area of some analog circuit design. A novel CMOS source-coupled backgate pair is proposed in this paper. The bulk of MOSFET is exploited and input devices are biased to operate in ohmic region. With this topology, the backgate pair of the wide linear input range and variable transconductance can be obtained. This backgate input differential stage is realized with the size of W/L=50/25 MOSFETs. The results show the nonlinear error is less than $\gamma$1% over 10V full-scale range for the bias current of 200$\mu$A with 10V single power-supply.
김윤태(YUN-TAE KIM),한우종(WOO-JONG HAN) 한국해양공학회 2008 韓國海洋工學會誌 Vol.22 No.4
The objective of this study was to investigate the mechanical characteristics of fiber-reinforced lightweight soil using waste fishing net or monofilament for recycling both dredged soils and bottom ash. Reinforced lightweight soil consists of dredged soil, cement, air foam, and bottom ash. Waste fishing net or monoiament was added the mixture in order to increase the shear strength of the lightweight soil. Test specimens were fabricated with various mixing conditions, including waste fishing net content and monofilament content. Several series of unconfined compression tests and direct shear tests were carried out. From the experimental results, it was found that the unconfined compressive strength, as well as the stress-strain behavior of reinforced lightweight soil was strongly influenced by mixing conditions. In this study, the maximum increase in shear strength was obtained with either a 0.5% content of monofilament or 0.25% waste fishing net. The unconfined compressive strength of reinforced lightweight soil with monofilament was greater than that of reinforced lightweight soil with waste fishing net.
메모리 상주 DBMS 기반의 OLTP 응용을 위한 다중프로세서 시스템 캐쉬 성능 분석
정용화(Yongwha Chung),한우종(Woo-Jong Hahn),윤석한(Suk-Han Yoon),박진원(Jin-Won Park),이강우(Kangwoo Lee),김양우(Yang Woo Kim) 한국정보과학회 2000 정보과학회 컴퓨팅의 실제 논문지 Vol.6 No.4
Currently, multiprocessors are evaluated almost exclusively with scientific applications. Commercial applications are rarely explored because it is difficult to obtain the source codes of commercial DBMS. Even when the source code is available, such as for POSTGRES, understanding the source code enough to perform detailed meaningful performance evaluations is a daunting task for computer architects. To evaluate multiprocessors with commercial applications, we have developed our own DBMS, called EZDB. EZDB is a parallelized DBMS, loosely inspired from POSTGRES, and running on top of a software architecture simulator. It is capable of executing parallel programs written in SQL. Contrary to POSTGRES, EZDB is not intended as a prototype for a production-quality DBMS. Its purpose is to easily run and evaluate the performance of commercial applications on multiprocessor architectures. To illustrate the usefulness of EZDB, we showed the cache performance data collected for the TPC-B benchmark on a shared-memory multiprocessor. The simulation results showed that the data structures exhibited unique sharing characteristics and that their locality properties and working sets were very different from those in scientific applications. 다중프로세서 시스템에 대한 대부분의 기존 연구는 과학계산용 응용을 중심으로 수행되어 왔으며, 또 다른 응용 분야인 상용 응용을 이용한 연구는 아직까지 초보 단계에 머물고 있는 실정이다. 이는 상용 DBMS의 소스 프로그램을 액세스하기가 쉽지 않으며, POSTGRES와 같은 공개된 소스 프로그램을 액세스 할 수 있더라도 컴퓨터 구조 설계자가 수십만 라인의 그 소스 프로그램을 이해하여 의미있는 성능분석을 수행하기는 사실상 불가능하기 때문이다. 본 연구에서는 상용 응용을 이용하여 다중프로세서 시스템을 분석하기 위하여, SQL로 작성된 병렬 프로그램을 아키텍처 시뮬레이터 상에서 수행할 수 있는 EZDB라는 병렬 DBMS를 자체 개발하였다. EZDB가 POSTGRES와 다른점은 그 목적이 다중프로세서 시스템에서 상용 응용을 수행시키고 그 성능을 쉽게 분석할 수 있다는 점이다. EZDB의 유용함을 확인하기 위해, 본 논문에서는 다중프로세서 시스템에서 TPC-B 작업부하를 수행시켰을 때의 캐쉬 성능을 분석한다. 구축된 작업부하를 기반으로 프로그램 구동 시뮬레이션을 수행한 결과, 상용 응용에서 데이터 구조의 공유 특성이 매우 특별하며 국부성 및 작업 세트가 과학계산 응용의 경우와 매우 상이함을 확인하였다.